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1 //===- subzero/src/IceTypes.def - X-macros for ICE types --------*- C++ -*-===// | 1 //===- subzero/src/IceTypes.def - X-macros for ICE types --------*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file defines properties of ICE primitive types in the form of | 10 // This file defines properties of ICE primitive types in the form of |
11 // x-macros. | 11 // x-macros. |
12 // | 12 // |
13 //===----------------------------------------------------------------------===// | 13 //===----------------------------------------------------------------------===// |
14 | 14 |
15 #ifndef SUBZERO_SRC_ICETYPES_DEF | 15 #ifndef SUBZERO_SRC_ICETYPES_DEF |
16 #define SUBZERO_SRC_ICETYPES_DEF | 16 #define SUBZERO_SRC_ICETYPES_DEF |
17 | 17 |
18 // Attributes of each target architecture. | 18 // Attributes of each target architecture. |
19 // NOTE on is_elf64 -- At some point NaCl would like to use ELF32 for all | 19 // NOTE on is_elf64 -- At some point NaCl would like to use ELF32 for all |
20 // ILP32 sandboxes, but for now the 64-bit architectures use ELF64: | 20 // ILP32 sandboxes, but for now the 64-bit architectures use ELF64: |
21 // https://code.google.com/p/nativeclient/issues/detail?id=349 | 21 // https://code.google.com/p/nativeclient/issues/detail?id=349 |
22 // TODO: Whoever adds AArch64 will need to set ABI e_flags. | 22 // TODO: Whoever adds AArch64 will need to set ABI e_flags. |
23 #define TARGETARCH_TABLE \ | 23 #define TARGETARCH_TABLE \ |
24 /* enum value, printable string, is_elf64, e_machine, e_flags */ \ | 24 /* enum value, printable string, is_elf64, e_machine, e_flags */ \ |
25 X(Target_X8632, "x86-32", false, EM_386, 0) \ | 25 X(Target_X8632, "x86-32", false, EM_386, 0) \ |
26 X(Target_X8664, "x86-64", true, EM_X86_64, 0) \ | 26 X(Target_X8664, "x86-64", true, EM_X86_64, 0) \ |
27 X(Target_ARM32, "arm32", false, EM_ARM, EF_ARM_EABI_VER5) \ | 27 X(Target_ARM32, "arm32", false, EM_ARM, EF_ARM_EABI_VER5) \ |
28 X(Target_ARM64, "arm64", true, EM_AARCH64, 0) \ | 28 X(Target_ARM64, "arm64", true, EM_AARCH64, 0) \ |
29 X(Target_MIPS32,"mips32", false, EM_MIPS, 0) \ | 29 X(Target_MIPS32, "mips32", false, EM_MIPS, 0) \ |
Jim Stichnoth
2015/06/12 18:03:14
fix column alignment, and also make sure the \ col
| |
30 //#define X(tag, str, is_elf64, e_machine, e_flags) | 30 //#define X(tag, str, is_elf64, e_machine, e_flags) |
31 | 31 |
32 #define ICETYPE_TABLE \ | 32 #define ICETYPE_TABLE \ |
33 /* enum value, size, align, # elts, element type, printable string */ \ | 33 /* enum value, size, align, # elts, element type, printable string */ \ |
34 /* (size and alignment in bytes) */ \ | 34 /* (size and alignment in bytes) */ \ |
35 X(IceType_void, 0, 0, 1, IceType_void, "void") \ | 35 X(IceType_void, 0, 0, 1, IceType_void, "void") \ |
36 X(IceType_i1, 1, 1, 1, IceType_i1, "i1") \ | 36 X(IceType_i1, 1, 1, 1, IceType_i1, "i1") \ |
37 X(IceType_i8, 1, 1, 1, IceType_i8, "i8") \ | 37 X(IceType_i8, 1, 1, 1, IceType_i8, "i8") \ |
38 X(IceType_i16, 2, 1, 1, IceType_i16, "i16") \ | 38 X(IceType_i16, 2, 1, 1, IceType_i16, "i16") \ |
39 X(IceType_i32, 4, 1, 1, IceType_i32, "i32") \ | 39 X(IceType_i32, 4, 1, 1, IceType_i32, "i32") \ |
(...skipping 30 matching lines...) Expand all Loading... | |
70 X(IceType_v4i1, 1, 1, 0, 0, 0, IceType_v4i1) \ | 70 X(IceType_v4i1, 1, 1, 0, 0, 0, IceType_v4i1) \ |
71 X(IceType_v8i1, 1, 1, 0, 0, 0, IceType_v8i1) \ | 71 X(IceType_v8i1, 1, 1, 0, 0, 0, IceType_v8i1) \ |
72 X(IceType_v16i1, 1, 1, 0, 0, 0, IceType_v16i1) \ | 72 X(IceType_v16i1, 1, 1, 0, 0, 0, IceType_v16i1) \ |
73 X(IceType_v16i8, 1, 1, 0, 1, 1, IceType_v16i1) \ | 73 X(IceType_v16i8, 1, 1, 0, 1, 1, IceType_v16i1) \ |
74 X(IceType_v8i16, 1, 1, 0, 1, 1, IceType_v8i1) \ | 74 X(IceType_v8i16, 1, 1, 0, 1, 1, IceType_v8i1) \ |
75 X(IceType_v4i32, 1, 1, 0, 1, 1, IceType_v4i1) \ | 75 X(IceType_v4i32, 1, 1, 0, 1, 1, IceType_v4i1) \ |
76 X(IceType_v4f32, 1, 0, 1, 0, 1, IceType_v4i1) \ | 76 X(IceType_v4f32, 1, 0, 1, 0, 1, IceType_v4i1) \ |
77 //#define X(tag, IsVec, IsInt, IsFloat, IsIntArith, IsLoadStore, CompareResult) | 77 //#define X(tag, IsVec, IsInt, IsFloat, IsIntArith, IsLoadStore, CompareResult) |
78 | 78 |
79 #endif // SUBZERO_SRC_ICETYPES_DEF | 79 #endif // SUBZERO_SRC_ICETYPES_DEF |
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