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Side by Side Diff: src/IceTargetLoweringX8632.cpp

Issue 1176133004: implement the null function for the Mips32 subzero compiler (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Run clang format Created 5 years, 6 months ago
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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the TargetLoweringX8632 class, which 10 // This file implements the TargetLoweringX8632 class, which
(...skipping 3101 matching lines...) Expand 10 before | Expand all | Expand 10 after
3112 Context.insert( 3112 Context.insert(
3113 InstFakeUse::create(Func, Context.getLastInserted()->getDest())); 3113 InstFakeUse::create(Func, Context.getLastInserted()->getDest()));
3114 return; 3114 return;
3115 } 3115 }
3116 case Intrinsics::AtomicRMW: 3116 case Intrinsics::AtomicRMW:
3117 if (!Intrinsics::isMemoryOrderValid( 3117 if (!Intrinsics::isMemoryOrderValid(
3118 ID, getConstantMemoryOrder(Instr->getArg(3)))) { 3118 ID, getConstantMemoryOrder(Instr->getArg(3)))) {
3119 Func->setError("Unexpected memory ordering for AtomicRMW"); 3119 Func->setError("Unexpected memory ordering for AtomicRMW");
3120 return; 3120 return;
3121 } 3121 }
3122 lowerAtomicRMW(Instr->getDest(), 3122 lowerAtomicRMW(
jvoung (off chromium) 2015/06/12 19:39:13 btw, what version of clang-format do you have? Is
3123 static_cast<uint32_t>(llvm::cast<ConstantInteger32>( 3123 Instr->getDest(),
3124 Instr->getArg(0))->getValue()), 3124 static_cast<uint32_t>(
3125 Instr->getArg(1), Instr->getArg(2)); 3125 llvm::cast<ConstantInteger32>(Instr->getArg(0))->getValue()),
3126 Instr->getArg(1), Instr->getArg(2));
3126 return; 3127 return;
3127 case Intrinsics::AtomicStore: { 3128 case Intrinsics::AtomicStore: {
3128 if (!Intrinsics::isMemoryOrderValid( 3129 if (!Intrinsics::isMemoryOrderValid(
3129 ID, getConstantMemoryOrder(Instr->getArg(2)))) { 3130 ID, getConstantMemoryOrder(Instr->getArg(2)))) {
3130 Func->setError("Unexpected memory ordering for AtomicStore"); 3131 Func->setError("Unexpected memory ordering for AtomicStore");
3131 return; 3132 return;
3132 } 3133 }
3133 // We require the memory address to be naturally aligned. 3134 // We require the memory address to be naturally aligned.
3134 // Given that is the case, then normal stores are atomic. 3135 // Given that is the case, then normal stores are atomic.
3135 // Add a fence after the store to make it visible. 3136 // Add a fence after the store to make it visible.
(...skipping 1874 matching lines...) Expand 10 before | Expand all | Expand 10 after
5010 case FT_Asm: 5011 case FT_Asm:
5011 case FT_Iasm: { 5012 case FT_Iasm: {
5012 OstreamLocker L(Ctx); 5013 OstreamLocker L(Ctx);
5013 emitConstantPool<PoolTypeConverter<float>>(Ctx); 5014 emitConstantPool<PoolTypeConverter<float>>(Ctx);
5014 emitConstantPool<PoolTypeConverter<double>>(Ctx); 5015 emitConstantPool<PoolTypeConverter<double>>(Ctx);
5015 } break; 5016 } break;
5016 } 5017 }
5017 } 5018 }
5018 5019
5019 } // end of namespace Ice 5020 } // end of namespace Ice
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