implement the null function for the Mips32 subzero compiler

tests_lit/llvm2ice_tests/function_aligned.ll

 ; Test that functions are aligned to the NaCl bundle alignment.
 ; We could be smarter and only do this for indirect call targets
 ; but typically you want to align functions anyway.
 ; Also, we are currently using hlts for non-executable padding.
 
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
 
 ; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented)
 ; once enough infrastructure is in. Also, switch to --filetype=obj
 ; when possible.
 ; RUN: %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command %p2i --filetype=asm --assemble \
 ; RUN:   --disassemble --target arm32 -i %s --args -O2 --skip-unimplemented \
 ; RUN:   | %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command FileCheck --check-prefix ARM32 %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN:   --command %p2i --filetype=asm --assemble \
+; RUN:   --disassemble --target mips32 -i %s --args -O2 --skip-unimplemented \
+; RUN:   | %if --need=target_MIPS32 --need=allow_dump \
+; RUN:   --command FileCheck --check-prefix MIPS32 %s
 
 define void @foo() {
   ret void
 }
 ; CHECK-LABEL: foo
 ; CHECK-NEXT: 0: {{.*}} ret
 ; CHECK-NEXT: 1: {{.*}} hlt
 ; ARM32-LABEL: foo
 ; ARM32-NEXT: 0: {{.*}} bx lr
 ; ARM32-NEXT: 4: e7fedef0 udf
 ; ARM32-NEXT: 8: e7fedef0 udf
 ; ARM32-NEXT: c: e7fedef0 udf
+; MIPS32-LABEL: foo
+; MIPS32: 4: {{.*}} jr ra

[jvoung (off chromium), 2015/07/08 16:44:26]

About "Is it possible to leave out the "-none-nacl" for now", the reason it
fails when you remove the "-none-nacl" is that this check is looking for "4:
{{.*}} jr ra". If it was starting at "0:" then that would work with non-nacl.

When the "check-lit" fails, it will print a whole slew of commands to reproduce
the failure, and one of them is the mips invocation. Copy that and try it
with/without the "-none-nacl". E.g.,

diff temp.nonnacl temp.nacl                                                     
                                                            (git)-[reeds_change]

2c2
< /tmp/tmpRYvxTG:     file format elf32-tradlittlemips-nacl
---
8,10c8,10
<    0:	03e00008 	jr	ra
<    4:	00000000 	nop
<    8:	e7fedef0 	swc1	$f30,-8464(ra)
---
14,15c14,16
<   10:	03e00008 	jr	ra
<   14:	00000000 	nop
---
The nacl version has the masking for ra prior to the jump, which is why it is at
4: instead of at 0:. Unlike ARM and X86, the LLVM assembler for MIPS applies
"auto-sandboxing". That is, besides inserting nops for alignment, it can also
insert masking instructions (the ARM and X86 assemblers don't do that yet...
since it can often involve a free register or reserving a register, it does
require some cooperation with the compiler).

Anyway, I'll help commit this as is, and you can adjust this in the next change,
if you agree with the assessment.

+; MIPS32-NEXT: 8: {{.*}} nop
+; MIPS32-NEXT: c: e7fedef0
 
 define void @bar() {
   ret void
 }
 ; CHECK-LABEL: bar
 ; CHECK-NEXT: 20: {{.*}} ret
 ; ARM32-LABEL: bar
 ; ARM32-NEXT: 10: {{.*}} bx lr
+; MIPS32-LABEL: bar
+; MIPS32: 14: {{.*}} jr ra
+; MIPS32-NEXT: 18: {{.*}} nop