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Side by Side Diff: src/IceInstMIPS32.h

Issue 1176133004: implement the null function for the Mips32 subzero compiler (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fixing patch per review comments Created 5 years, 5 months ago
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1 //===- subzero/src/IceInstMIPS32.h - MIPS32 machine instrs --*- C++ -*-=== // 1 //===- subzero/src/IceInstMIPS32.h - MIPS32 machine instrs --*- C++ -*-=== //
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
11 /// This file declares the InstMIPS32 and OperandMIPS32 classes and 11 /// This file declares the InstMIPS32 and OperandMIPS32 classes and
12 /// their subclasses. This represents the machine instructions and 12 /// their subclasses. This represents the machine instructions and
13 /// operands used for MIPS32 code selection. 13 /// operands used for MIPS32 code selection.
14 /// 14 ///
15 //===----------------------------------------------------------------------===// 15 //===----------------------------------------------------------------------===//
16 16
17 #ifndef SUBZERO_SRC_ICEINSTMIPS32_H 17 #ifndef SUBZERO_SRC_ICEINSTMIPS32_H
18 #define SUBZERO_SRC_ICEINSTMIPS32_H 18 #define SUBZERO_SRC_ICEINSTMIPS32_H
19 19
20 #include "IceDefs.h" 20 #include "IceDefs.h"
21 #include "IceInst.h"
22 #include "IceInstMIPS32.def"
23 #include "IceOperand.h"
21 24
22 namespace Ice { 25 namespace Ice {
23 26
24 class TargetMIPS32; 27 class TargetMIPS32;
25 // Fill this in. 28
29 // Base class for Mips instructions.
30 class InstMIPS32 : public InstTarget {
31 InstMIPS32() = delete;
32 InstMIPS32(const InstMIPS32 &) = delete;
33 InstMIPS32 &operator=(const InstMIPS32 &) = delete;
34
35 public:
36 enum InstKindMIPS32 { k__Start = Inst::Target, Ret };
37
38 static const char *getWidthString(Type Ty);
39
40 void dump(const Cfg *Func) const override;
41
42 protected:
43 InstMIPS32(Cfg *Func, InstKindMIPS32 Kind, SizeT Maxsrcs, Variable *Dest)
44 : InstTarget(Func, static_cast<InstKind>(Kind), Maxsrcs, Dest) {}
45 ~InstMIPS32() override {}
46 static bool isClassof(const Inst *Inst, InstKindMIPS32 MyKind) {
47 return Inst->getKind() == static_cast<InstKind>(MyKind);
48 }
49 };
50
51 // Ret pseudo-instruction. This is actually a "jr" instruction with
52 // an "ra" register operand, but epilogue lowering will search for a Ret
53 // instead of a generic "jr". This instruction also takes a Source
54 // operand (for non-void returning functions) for liveness analysis, though
55 // a FakeUse before the ret would do just as well.
56 // This needs was take from the ARM port and needs to be scrubbed in the future
57 // TODO(reed kotler)
58 //
59 class InstMIPS32Ret : public InstMIPS32 {
60
61 InstMIPS32Ret() = delete;
62 InstMIPS32Ret(const InstMIPS32Ret &) = delete;
63 InstMIPS32Ret &operator=(const InstMIPS32Ret &) = delete;
64
65 public:
66 static InstMIPS32Ret *create(Cfg *Func, Variable *RA,
67 Variable *Source = nullptr) {
68 return new (Func->allocate<InstMIPS32Ret>())
69 InstMIPS32Ret(Func, RA, Source);
70 }
71 void emit(const Cfg *Func) const override;
72 void emitIAS(const Cfg *Func) const override;
73 void dump(const Cfg *Func) const override;
74 static bool classof(const Inst *Inst) { return isClassof(Inst, Ret); }
75
76 private:
77 InstMIPS32Ret(Cfg *Func, Variable *RA, Variable *Source);
78 ~InstMIPS32Ret() override {}
79 };
26 80
27 } // end of namespace Ice 81 } // end of namespace Ice
28 82
29 #endif // SUBZERO_SRC_ICEINSTMIPS32_H 83 #endif // SUBZERO_SRC_ICEINSTMIPS32_H
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