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Side by Side Diff: runtime/vm/intermediate_language_arm.cc

Issue 1174173007: Expand the class id to 32 bits and size field to 16 bits on 64-bit platforms. (Closed) Base URL: git@github.com:dart-lang/sdk.git@master
Patch Set: Created 5 years, 6 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM.
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/intermediate_language.h" 8 #include "vm/intermediate_language.h"
9 9
10 #include "vm/cpu.h" 10 #include "vm/cpu.h"
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1564 1564
1565 for (intptr_t i = 0; i < num_temps; i++) { 1565 for (intptr_t i = 0; i < num_temps; i++) {
1566 summary->set_temp(i, Location::RequiresRegister()); 1566 summary->set_temp(i, Location::RequiresRegister());
1567 } 1567 }
1568 1568
1569 return summary; 1569 return summary;
1570 } 1570 }
1571 1571
1572 1572
1573 void GuardFieldClassInstr::EmitNativeCode(FlowGraphCompiler* compiler) { 1573 void GuardFieldClassInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
1574 ASSERT(sizeof(classid_t) == 2);
siva 2015/06/12 22:08:11 instead of 2 use kInt16Size
1575
1574 const intptr_t value_cid = value()->Type()->ToCid(); 1576 const intptr_t value_cid = value()->Type()->ToCid();
1575 const intptr_t field_cid = field().guarded_cid(); 1577 const intptr_t field_cid = field().guarded_cid();
1576 const intptr_t nullability = field().is_nullable() ? kNullCid : kIllegalCid; 1578 const intptr_t nullability = field().is_nullable() ? kNullCid : kIllegalCid;
1577 1579
1578 if (field_cid == kDynamicCid) { 1580 if (field_cid == kDynamicCid) {
1579 ASSERT(!compiler->is_optimizing()); 1581 ASSERT(!compiler->is_optimizing());
1580 return; // Nothing to emit. 1582 return; // Nothing to emit.
1581 } 1583 }
1582 1584
1583 const bool emit_full_guard = 1585 const bool emit_full_guard =
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2027 BoxAllocationSlowPath::Allocate( 2029 BoxAllocationSlowPath::Allocate(
2028 compiler, instruction, cls, box_reg, temp); 2030 compiler, instruction, cls, box_reg, temp);
2029 2031
2030 __ MoveRegister(temp, box_reg); 2032 __ MoveRegister(temp, box_reg);
2031 __ StoreIntoObjectOffset(instance_reg, offset, temp); 2033 __ StoreIntoObjectOffset(instance_reg, offset, temp);
2032 __ Bind(&done); 2034 __ Bind(&done);
2033 } 2035 }
2034 2036
2035 2037
2036 void StoreInstanceFieldInstr::EmitNativeCode(FlowGraphCompiler* compiler) { 2038 void StoreInstanceFieldInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
2039 ASSERT(sizeof(classid_t) == 2);
2040
2037 Label skip_store; 2041 Label skip_store;
2038 2042
2039 const Register instance_reg = locs()->in(0).reg(); 2043 const Register instance_reg = locs()->in(0).reg();
2040 2044
2041 if (IsUnboxedStore() && compiler->is_optimizing()) { 2045 if (IsUnboxedStore() && compiler->is_optimizing()) {
2042 const DRegister value = EvenDRegisterOf(locs()->in(1).fpu_reg()); 2046 const DRegister value = EvenDRegisterOf(locs()->in(1).fpu_reg());
2043 const Register temp = locs()->temp(0).reg(); 2047 const Register temp = locs()->temp(0).reg();
2044 const Register temp2 = locs()->temp(1).reg(); 2048 const Register temp2 = locs()->temp(1).reg();
2045 const intptr_t cid = field().UnboxedFieldCid(); 2049 const intptr_t cid = field().UnboxedFieldCid();
2046 2050
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2420 : Location::FpuRegisterLocation(Q1)); 2424 : Location::FpuRegisterLocation(Q1));
2421 locs->set_temp(1, Location::RequiresRegister()); 2425 locs->set_temp(1, Location::RequiresRegister());
2422 locs->set_temp(2, Location::RequiresRegister()); 2426 locs->set_temp(2, Location::RequiresRegister());
2423 } 2427 }
2424 locs->set_out(0, Location::RequiresRegister()); 2428 locs->set_out(0, Location::RequiresRegister());
2425 return locs; 2429 return locs;
2426 } 2430 }
2427 2431
2428 2432
2429 void LoadFieldInstr::EmitNativeCode(FlowGraphCompiler* compiler) { 2433 void LoadFieldInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
2434 ASSERT(sizeof(classid_t) == 2);
2435
2430 const Register instance_reg = locs()->in(0).reg(); 2436 const Register instance_reg = locs()->in(0).reg();
2431 if (IsUnboxedLoad() && compiler->is_optimizing()) { 2437 if (IsUnboxedLoad() && compiler->is_optimizing()) {
2432 const DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg()); 2438 const DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
2433 const Register temp = locs()->temp(0).reg(); 2439 const Register temp = locs()->temp(0).reg();
2434 __ ldr(temp, FieldAddress(instance_reg, offset_in_bytes())); 2440 __ ldr(temp, FieldAddress(instance_reg, offset_in_bytes()));
2435 const intptr_t cid = field()->UnboxedFieldCid(); 2441 const intptr_t cid = field()->UnboxedFieldCid();
2436 switch (cid) { 2442 switch (cid) {
2437 case kDoubleCid: 2443 case kDoubleCid:
2438 __ Comment("UnboxedDoubleLoadFieldInstr"); 2444 __ Comment("UnboxedDoubleLoadFieldInstr");
2439 __ LoadDFromOffset(result, temp, 2445 __ LoadDFromOffset(result, temp,
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6879 1, 6885 1,
6880 locs()); 6886 locs());
6881 __ Drop(1); 6887 __ Drop(1);
6882 __ Pop(result); 6888 __ Pop(result);
6883 } 6889 }
6884 6890
6885 6891
6886 } // namespace dart 6892 } // namespace dart
6887 6893
6888 #endif // defined TARGET_ARCH_ARM 6894 #endif // defined TARGET_ARCH_ARM
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