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1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// | 1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// |
2 // | 2 // |
3 // The LLVM Compiler Infrastructure | 3 // The LLVM Compiler Infrastructure |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file contains the base ARM implementation of TargetRegisterInfo class. | 10 // This file contains the base ARM implementation of TargetRegisterInfo class. |
11 // | 11 // |
12 //===----------------------------------------------------------------------===// | 12 //===----------------------------------------------------------------------===// |
13 | 13 |
14 #include "ARMBaseRegisterInfo.h" | 14 #include "ARMBaseRegisterInfo.h" |
15 #include "ARM.h" | 15 #include "ARM.h" |
16 #include "ARMBaseInstrInfo.h" | 16 #include "ARMBaseInstrInfo.h" |
17 #include "ARMFrameLowering.h" | 17 #include "ARMFrameLowering.h" |
18 #include "ARMMachineFunctionInfo.h" | 18 #include "ARMMachineFunctionInfo.h" |
19 #include "ARMSubtarget.h" | 19 #include "ARMSubtarget.h" |
20 #include "MCTargetDesc/ARMAddressingModes.h" | 20 #include "MCTargetDesc/ARMAddressingModes.h" |
21 #include "llvm/ADT/BitVector.h" | 21 #include "llvm/ADT/BitVector.h" |
22 #include "llvm/ADT/SmallVector.h" | 22 #include "llvm/ADT/SmallVector.h" |
23 #include "llvm/CodeGen/MachineConstantPool.h" | 23 #include "llvm/CodeGen/MachineConstantPool.h" |
24 #include "llvm/CodeGen/MachineFrameInfo.h" | 24 #include "llvm/CodeGen/MachineFrameInfo.h" |
25 #include "llvm/CodeGen/MachineFunction.h" | 25 #include "llvm/CodeGen/MachineFunction.h" |
26 #include "llvm/CodeGen/MachineInstrBuilder.h" | 26 #include "llvm/CodeGen/MachineInstrBuilder.h" |
27 #include "llvm/CodeGen/MachineModuleInfo.h" // @LOCALMOD | |
28 #include "llvm/CodeGen/MachineRegisterInfo.h" | 27 #include "llvm/CodeGen/MachineRegisterInfo.h" |
29 #include "llvm/CodeGen/RegisterScavenging.h" | 28 #include "llvm/CodeGen/RegisterScavenging.h" |
30 #include "llvm/CodeGen/VirtRegMap.h" | 29 #include "llvm/CodeGen/VirtRegMap.h" |
31 #include "llvm/IR/Constants.h" | 30 #include "llvm/IR/Constants.h" |
32 #include "llvm/IR/DerivedTypes.h" | 31 #include "llvm/IR/DerivedTypes.h" |
33 #include "llvm/IR/Function.h" | 32 #include "llvm/IR/Function.h" |
34 #include "llvm/IR/LLVMContext.h" | 33 #include "llvm/IR/LLVMContext.h" |
35 #include "llvm/Support/Debug.h" | 34 #include "llvm/Support/Debug.h" |
36 #include "llvm/Support/ErrorHandling.h" | 35 #include "llvm/Support/ErrorHandling.h" |
37 #include "llvm/Support/raw_ostream.h" | 36 #include "llvm/Support/raw_ostream.h" |
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57 return ARM::R11; | 56 return ARM::R11; |
58 } else if (STI.isTargetWindows()) | 57 } else if (STI.isTargetWindows()) |
59 return ARM::R11; | 58 return ARM::R11; |
60 else // ARM EABI | 59 else // ARM EABI |
61 return STI.isThumb() ? ARM::R7 : ARM::R11; | 60 return STI.isThumb() ? ARM::R7 : ARM::R11; |
62 } | 61 } |
63 | 62 |
64 const MCPhysReg* | 63 const MCPhysReg* |
65 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { | 64 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
66 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>(); | 65 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>(); |
67 // @LOCALMOD-START | 66 if (STI.isTargetNaCl()) return CSR_NaCl_SaveList; // @LOCALMOD |
68 // We don't support special calling conventions for NaCl here. | |
69 if (STI.isTargetNaCl()) { | |
70 if (MF->getMMI().callsEHReturn()) | |
71 return CSR_NaCl_EHRet_SaveList; | |
72 return CSR_NaCl_SaveList; | |
73 } | |
74 // @LOCALMOD-END | |
75 | 67 |
76 const MCPhysReg *RegList = | 68 const MCPhysReg *RegList = |
77 STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; | 69 STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; |
78 | 70 |
79 const Function *F = MF->getFunction(); | 71 const Function *F = MF->getFunction(); |
80 if (F->getCallingConv() == CallingConv::GHC) { | 72 if (F->getCallingConv() == CallingConv::GHC) { |
81 // GHC set of callee saved regs is empty as all those regs are | 73 // GHC set of callee saved regs is empty as all those regs are |
82 // used for passing STG regs around | 74 // used for passing STG regs around |
83 return CSR_NoRegs_SaveList; | 75 return CSR_NoRegs_SaveList; |
84 } else if (F->hasFnAttribute("interrupt")) { | 76 } else if (F->hasFnAttribute("interrupt")) { |
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823 // In practice the SizeMultiplier will only factor in for straight line code | 815 // In practice the SizeMultiplier will only factor in for straight line code |
824 // that uses a lot of NEON vectors, which isn't terribly common. | 816 // that uses a lot of NEON vectors, which isn't terribly common. |
825 unsigned SizeMultiplier = MBB->size()/100; | 817 unsigned SizeMultiplier = MBB->size()/100; |
826 SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1; | 818 SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1; |
827 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) { | 819 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) { |
828 It->second += NewRCWeight.RegWeight; | 820 It->second += NewRCWeight.RegWeight; |
829 return true; | 821 return true; |
830 } | 822 } |
831 return false; | 823 return false; |
832 } | 824 } |
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