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Side by Side Diff: source/libvpx/vp9/encoder/x86/vp9_error_intrin_avx2.c

Issue 1162573005: libvpx: Pull from upstream (Closed) Base URL: https://chromium.googlesource.com/chromium/deps/libvpx.git@master
Patch Set: Created 5 years, 6 months ago
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1 /* 1 /*
2 * Copyright (c) 2014 The WebM project authors. All Rights Reserved. 2 * Copyright (c) 2014 The WebM project authors. All Rights Reserved.
3 * 3 *
4 * Usee of this source code is governed by a BSD-style license 4 * Usee of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source 5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found 6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may 7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree. 8 * be found in the AUTHORS file in the root of the source tree.
9 */ 9 */
10 10
11 #include <immintrin.h> // AVX2 11 #include <immintrin.h> // AVX2
12
13 #include "./vp9_rtcd.h"
12 #include "vpx/vpx_integer.h" 14 #include "vpx/vpx_integer.h"
13 15
14
15 int64_t vp9_block_error_avx2(const int16_t *coeff, 16 int64_t vp9_block_error_avx2(const int16_t *coeff,
16 const int16_t *dqcoeff, 17 const int16_t *dqcoeff,
17 intptr_t block_size, 18 intptr_t block_size,
18 int64_t *ssz) { 19 int64_t *ssz) {
19 __m256i sse_reg, ssz_reg, coeff_reg, dqcoeff_reg; 20 __m256i sse_reg, ssz_reg, coeff_reg, dqcoeff_reg;
20 __m256i exp_dqcoeff_lo, exp_dqcoeff_hi, exp_coeff_lo, exp_coeff_hi; 21 __m256i exp_dqcoeff_lo, exp_dqcoeff_hi, exp_coeff_lo, exp_coeff_hi;
21 __m256i sse_reg_64hi, ssz_reg_64hi; 22 __m256i sse_reg_64hi, ssz_reg_64hi;
22 __m128i sse_reg128, ssz_reg128; 23 __m128i sse_reg128, ssz_reg128;
23 int64_t sse; 24 int64_t sse;
24 int i; 25 int i;
(...skipping 38 matching lines...) Expand 10 before | Expand all | Expand 10 after
63 64
64 ssz_reg128 = _mm_add_epi64(_mm256_castsi256_si128(ssz_reg), 65 ssz_reg128 = _mm_add_epi64(_mm256_castsi256_si128(ssz_reg),
65 _mm256_extractf128_si256(ssz_reg, 1)); 66 _mm256_extractf128_si256(ssz_reg, 1));
66 67
67 // store the results 68 // store the results
68 _mm_storel_epi64((__m128i*)(&sse), sse_reg128); 69 _mm_storel_epi64((__m128i*)(&sse), sse_reg128);
69 70
70 _mm_storel_epi64((__m128i*)(ssz), ssz_reg128); 71 _mm_storel_epi64((__m128i*)(ssz), ssz_reg128);
71 return sse; 72 return sse;
72 } 73 }
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