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1 /* | 1 /* |
2 * Copyright (c) 2013 The WebM project authors. All Rights Reserved. | 2 * Copyright (c) 2013 The WebM project authors. All Rights Reserved. |
3 * | 3 * |
4 * Use of this source code is governed by a BSD-style license | 4 * Use of this source code is governed by a BSD-style license |
5 * that can be found in the LICENSE file in the root of the source | 5 * that can be found in the LICENSE file in the root of the source |
6 * tree. An additional intellectual property rights grant can be found | 6 * tree. An additional intellectual property rights grant can be found |
7 * in the file PATENTS. All contributing project authors may | 7 * in the file PATENTS. All contributing project authors may |
8 * be found in the AUTHORS file in the root of the source tree. | 8 * be found in the AUTHORS file in the root of the source tree. |
9 */ | 9 */ |
10 | 10 |
11 #include <assert.h> | 11 #include <assert.h> |
12 #include <stdio.h> | 12 #include <stdio.h> |
13 | 13 |
14 #include "./vpx_config.h" | 14 #include "./vpx_config.h" |
15 #include "./vp9_rtcd.h" | 15 #include "./vp9_rtcd.h" |
| 16 #include "vpx_ports/mem.h" |
16 #include "vp9/common/vp9_common.h" | 17 #include "vp9/common/vp9_common.h" |
17 #include "vp9/common/vp9_blockd.h" | 18 #include "vp9/common/vp9_blockd.h" |
18 #include "vp9/common/vp9_idct.h" | 19 #include "vp9/common/vp9_idct.h" |
19 #include "vp9/common/mips/dspr2/vp9_common_dspr2.h" | 20 #include "vp9/common/mips/dspr2/vp9_common_dspr2.h" |
20 | 21 |
21 #if HAVE_DSPR2 | 22 #if HAVE_DSPR2 |
22 static void idct16_rows_dspr2(const int16_t *input, int16_t *output, | 23 static void idct16_rows_dspr2(const int16_t *input, int16_t *output, |
23 uint32_t no_rows) { | 24 uint32_t no_rows) { |
24 int i; | 25 int i; |
25 int step1_0, step1_1, step1_2, step1_3, step1_4, step1_5, step1_6, step1_7; | 26 int step1_0, step1_1, step1_2, step1_3, step1_4, step1_5, step1_6, step1_7; |
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1306 : [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3), [t4] "=&r" (t4), | 1307 : [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3), [t4] "=&r" (t4), |
1307 [vector_1] "=&r" (vector_1), [vector_2] "=&r" (vector_2), | 1308 [vector_1] "=&r" (vector_1), [vector_2] "=&r" (vector_2), |
1308 [vector_3] "=&r" (vector_3), [vector_4] "=&r" (vector_4), | 1309 [vector_3] "=&r" (vector_3), [vector_4] "=&r" (vector_4), |
1309 [dest] "+&r" (dest) | 1310 [dest] "+&r" (dest) |
1310 : [dest_stride] "r" (dest_stride), [vector_a1] "r" (vector_a1) | 1311 : [dest_stride] "r" (dest_stride), [vector_a1] "r" (vector_a1) |
1311 ); | 1312 ); |
1312 } | 1313 } |
1313 } | 1314 } |
1314 } | 1315 } |
1315 #endif // #if HAVE_DSPR2 | 1316 #endif // #if HAVE_DSPR2 |
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