ARM64: Work around Clang's inline assembly limitations.

src/base/atomicops_internals_arm64_gcc.h

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // This file is an internal atomic implementation, use atomicops.h instead.
 
 #ifndef V8_BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_
 #define V8_BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_
 
 namespace v8 {
@@ skipping 21 matching lines @@
     "0:                                    \n\t"
     "ldxr %w[prev], %[ptr]                 \n\t"  // Load the previous value.
     "cmp %w[prev], %w[old_value]           \n\t"
     "bne 1f                                \n\t"
     "stxr %w[temp], %w[new_value], %[ptr]  \n\t"  // Try to store the new value.
     "cbnz %w[temp], 0b                     \n\t"  // Retry if it did not work.
     "1:                                    \n\t"
     : [prev]"=&r" (prev),
       [temp]"=&r" (temp),
       [ptr]"+Q" (*ptr)
+#ifdef __clang__
+    // Workaround for Clang (https://llvm.org/bugs/show_bug.cgi?id=23575).
+    : [old_value]"Ir" (old_value),
+#else
     : [old_value]"IJr" (old_value),
+#endif
       [new_value]"r" (new_value)
     : "cc", "memory"
   );  // NOLINT
 
   return prev;
 }
 
 inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
                                          Atomic32 new_value) {
   Atomic32 result;
@@ skipping 21 matching lines @@
 
   __asm__ __volatile__ (  // NOLINT
     "0:                                       \n\t"
     "ldxr %w[result], %[ptr]                  \n\t"  // Load the previous value.
     "add %w[result], %w[result], %w[increment]\n\t"
     "stxr %w[temp], %w[result], %[ptr]        \n\t"  // Try to store the result.
     "cbnz %w[temp], 0b                        \n\t"  // Retry on failure.
     : [result]"=&r" (result),
       [temp]"=&r" (temp),
       [ptr]"+Q" (*ptr)
+#ifdef __clang__
+    // Workaround for Clang (https://llvm.org/bugs/show_bug.cgi?id=23575).
+    : [increment]"Ir" (increment)
+#else
     : [increment]"IJr" (increment)
+#endif
     : "memory"
   );  // NOLINT
 
   return result;
 }
 
 inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
                                         Atomic32 increment) {
   Atomic32 result;
 
@@ skipping 87 matching lines @@
     "0:                                    \n\t"
     "ldxr %[prev], %[ptr]                  \n\t"
     "cmp %[prev], %[old_value]             \n\t"
     "bne 1f                                \n\t"
     "stxr %w[temp], %[new_value], %[ptr]   \n\t"
     "cbnz %w[temp], 0b                     \n\t"
     "1:                                    \n\t"
     : [prev]"=&r" (prev),
       [temp]"=&r" (temp),
       [ptr]"+Q" (*ptr)
+#ifdef __clang__
+    // Workaround for Clang (https://llvm.org/bugs/show_bug.cgi?id=23575).
+    : [old_value]"Ir" (old_value),
+#else
     : [old_value]"IJr" (old_value),
+#endif
       [new_value]"r" (new_value)
     : "cc", "memory"
   );  // NOLINT
 
   return prev;
 }
 
 inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
                                          Atomic64 new_value) {
   Atomic64 result;
@@ skipping 21 matching lines @@
 
   __asm__ __volatile__ (  // NOLINT
     "0:                                     \n\t"
     "ldxr %[result], %[ptr]                 \n\t"
     "add %[result], %[result], %[increment] \n\t"
     "stxr %w[temp], %[result], %[ptr]       \n\t"
     "cbnz %w[temp], 0b                      \n\t"
     : [result]"=&r" (result),
       [temp]"=&r" (temp),
       [ptr]"+Q" (*ptr)
+#ifdef __clang__
+    // Workaround for Clang (https://llvm.org/bugs/show_bug.cgi?id=23575).
+    : [increment]"Ir" (increment)
+#else
     : [increment]"IJr" (increment)
+#endif
     : "memory"
   );  // NOLINT
 
   return result;
 }
 
 inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
                                         Atomic64 increment) {
   Atomic64 result;
 
@@ skipping 62 matching lines @@
 }
 
 inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
   MemoryBarrier();
   return *ptr;
 }
 
 } }  // namespace v8::base
 
 #endif  // V8_BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_