Subzero: Changes needed for LLVM 3.7 integration.

tests_lit/llvm2ice_tests/address-mode-opt.ll

Index: tests_lit/llvm2ice_tests/address-mode-opt.ll
diff --git a/tests_lit/llvm2ice_tests/address-mode-opt.ll b/tests_lit/llvm2ice_tests/address-mode-opt.ll
index 6f196c9b1c6c75c498955c8ab0b8cc0326c1b524..1c929f82cac583130e0478b9d47d505db50a2102 100644
--- a/tests_lit/llvm2ice_tests/address-mode-opt.ll
+++ b/tests_lit/llvm2ice_tests/address-mode-opt.ll
@@ -10,7 +10,7 @@ entry:
   %arg.int = ptrtoint float* %arg to i32
   %addr.int = add i32 %arg.int, 200000
   %addr.ptr = inttoptr i32 %addr.int to float*
-  %addr.load = load float* %addr.ptr, align 4
+  %addr.load = load float, float* %addr.ptr, align 4
   ret float %addr.load
 ; CHECK-LABEL: load_arg_plus_200000
 ; CHECK: movss xmm0,DWORD PTR [eax+0x30d40]
@@ -21,7 +21,7 @@ entry:
   %arg.int = ptrtoint float* %arg to i32
   %addr.int = add i32 200000, %arg.int
   %addr.ptr = inttoptr i32 %addr.int to float*
-  %addr.load = load float* %addr.ptr, align 4
+  %addr.load = load float, float* %addr.ptr, align 4
   ret float %addr.load
 ; CHECK-LABEL: load_200000_plus_arg
 ; CHECK: movss xmm0,DWORD PTR [eax+0x30d40]
@@ -32,7 +32,7 @@ entry:
   %arg.int = ptrtoint float* %arg to i32
   %addr.int = sub i32 %arg.int, 200000
   %addr.ptr = inttoptr i32 %addr.int to float*
-  %addr.load = load float* %addr.ptr, align 4
+  %addr.load = load float, float* %addr.ptr, align 4
   ret float %addr.load
 ; CHECK-LABEL: load_arg_minus_200000
 ; CHECK: movss xmm0,DWORD PTR [eax-0x30d40]
@@ -43,7 +43,7 @@ entry:
   %arg.int = ptrtoint float* %arg to i32
   %addr.int = sub i32 200000, %arg.int
   %addr.ptr = inttoptr i32 %addr.int to float*
-  %addr.load = load float* %addr.ptr, align 4
+  %addr.load = load float, float* %addr.ptr, align 4
   ret float %addr.load
 ; CHECK-LABEL: load_200000_minus_arg
 ; CHECK: movss xmm0,DWORD PTR [e{{..}}]
@@ -53,7 +53,7 @@ define <8 x i16> @load_mul_v8i16_mem(<8 x i16> %arg0, i32 %arg1_iptr) {
 entry:
   %addr_sub = sub i32 %arg1_iptr, 200000
   %addr_ptr = inttoptr i32 %addr_sub to <8 x i16>*
-  %arg1 = load <8 x i16>* %addr_ptr, align 2
+  %arg1 = load <8 x i16>, <8 x i16>* %addr_ptr, align 2
   %res_vec = mul <8 x i16> %arg0, %arg1
   ret <8 x i16> %res_vec
 ; Address mode optimization is generally unsafe for SSE vector instructions.
@@ -65,7 +65,7 @@ define <4 x i32> @load_mul_v4i32_mem(<4 x i32> %arg0, i32 %arg1_iptr) {
 entry:
   %addr_sub = sub i32 %arg1_iptr, 200000
   %addr_ptr = inttoptr i32 %addr_sub to <4 x i32>*
-  %arg1 = load <4 x i32>* %addr_ptr, align 4
+  %arg1 = load <4 x i32>, <4 x i32>* %addr_ptr, align 4
   %res = mul <4 x i32> %arg0, %arg1
   ret <4 x i32> %res
 ; Address mode optimization is generally unsafe for SSE vector instructions.
@@ -83,7 +83,7 @@ entry:
   %addr1.int = add i32 12, %arg.int
   %addr2.int = sub i32 %addr1.int, 4
   %addr2.ptr = inttoptr i32 %addr2.int to float*
-  %addr2.load = load float* %addr2.ptr, align 4
+  %addr2.load = load float, float* %addr2.ptr, align 4
   ret float %addr2.load
 ; CHECK-LABEL: address_mode_opt_chaining
 ; CHECK: movss xmm0,DWORD PTR [eax+0x8]
@@ -95,7 +95,7 @@ entry:
   %addr1.int = add i32 2147483640, %arg.int
   %addr2.int = add i32 %addr1.int, 2147483643
   %addr2.ptr = inttoptr i32 %addr2.int to float*
-  %addr2.load = load float* %addr2.ptr, align 4
+  %addr2.load = load float, float* %addr2.ptr, align 4
   ret float %addr2.load
 ; CHECK-LABEL: address_mode_opt_chaining_overflow
 ; CHECK: 0x7ffffff8
@@ -108,7 +108,7 @@ entry:
   %addr1.int = sub i32 %arg.int, 2147483640
   %addr2.int = sub i32 %addr1.int, 2147483643
   %addr2.ptr = inttoptr i32 %addr2.int to float*
-  %addr2.load = load float* %addr2.ptr, align 4
+  %addr2.load = load float, float* %addr2.ptr, align 4
   ret float %addr2.load
 ; CHECK-LABEL: address_mode_opt_chaining_overflow_sub
 ; CHECK: 0x7ffffff8
@@ -121,7 +121,7 @@ entry:
   %addr1.int = sub i32 %arg.int, 2147483640
   %addr2.int = add i32 %addr1.int, 2147483643
   %addr2.ptr = inttoptr i32 %addr2.int to float*
-  %addr2.load = load float* %addr2.ptr, align 4
+  %addr2.load = load float, float* %addr2.ptr, align 4
   ret float %addr2.load
 ; CHECK-LABEL: address_mode_opt_chaining_no_overflow
 ; CHECK: movss xmm0,DWORD PTR [{{.*}}+0x3]
@@ -132,7 +132,7 @@ entry:
   %arg.int = ptrtoint float* %arg to i32
   %addr1.int = add i32 %arg.int, 2147483648
   %addr1.ptr = inttoptr i32 %addr1.int to float*
-  %addr1.load = load float* %addr1.ptr, align 4
+  %addr1.load = load float, float* %addr1.ptr, align 4
   ret float %addr1.load
 ; CHECK-LABEL: address_mode_opt_add_pos_min_int
 ; CHECK: movss xmm0,DWORD PTR [{{.*}}-0x80000000]
@@ -143,7 +143,7 @@ entry:
   %arg.int = ptrtoint float* %arg to i32
   %addr1.int = sub i32 %arg.int, 2147483648
   %addr1.ptr = inttoptr i32 %addr1.int to float*
-  %addr1.load = load float* %addr1.ptr, align 4
+  %addr1.load = load float, float* %addr1.ptr, align 4
   ret float %addr1.load
 ; CHECK-LABEL: address_mode_opt_sub_min_int
 ; CHECK: movss xmm0,DWORD PTR [{{.*}}-0x80000000]