Subzero: Changes needed for LLVM 3.7 integration.

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 \
@@ skipping 1273 matching lines @@
 ; OPTM1-LABEL: icmpUle64Bool
 ; OPTM1: cmp
 ; OPTM1: jb
 ; OPTM1: ja
 ; OPTM1: cmp
 ; OPTM1: jbe
 
 define internal i64 @load64(i32 %a) {
 entry:
   %__1 = inttoptr i32 %a to i64*
-  %v0 = load i64* %__1, align 1
+  %v0 = load i64, i64* %__1, align 1
   ret i64 %v0
 }
 ; CHECK-LABEL: load64
 ; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
 ; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]]
 ; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]+0x4]
 ;
 ; OPTM1-LABEL: load64
 ; OPTM1: mov e{{..}},DWORD PTR [e{{..}}]
 ; OPTM1: mov e{{..}},DWORD PTR [e{{..}}+0x4]
@@ skipping 150 matching lines @@
   ret void
 }
 ; The following checks are not strictly necessary since one of the RUN
 ; lines actually runs the output through the assembler.
 ; CHECK-LABEL: icmpLt64Imm
 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
 ; OPTM1-LABEL: icmpLt64Imm
 ; OPTM1-NOT: cmp 0x{{[0-9a-f]+}},
 ; ARM32-LABEL: icmpLt64Imm
 ; ARM32-NOT: cmp #{{[0-9a-f]+}},