Subzero: Changes needed for LLVM 3.7 integration.

tests_lit/assembler/x86/opcode_register_encodings.ll

 ; Tests various aspects of x86 opcode encodings. E.g., some opcodes like
 ; those for pmull vary more wildly depending on operand size (rather than
 ; follow a usual pattern).
 
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 -mattr=sse4.1 \
 ; RUN:  -sandbox | FileCheck %s
 
 define <8 x i16> @test_mul_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
 entry:
   %res = mul <8 x i16> %arg0, %arg1
@@ skipping 97 matching lines @@
   store <16 x i8> %v, <16 x i8>* %addr3_v16xI8, align 1
   ret void
 }
 ; CHECK-LABEL: store_v16xI8
 ; CHECK: 0f 11 0{{.*}} movups XMMWORD PTR [e{{.*}}],xmm0
 
 define <16 x i8> @load_v16xI8(i32 %addr, i32 %addr2, i32 %addr3) {
   %addr_v16xI8 = inttoptr i32 %addr to <16 x i8>*
   %addr2_v16xI8 = inttoptr i32 %addr2 to <16 x i8>*
   %addr3_v16xI8 = inttoptr i32 %addr3 to <16 x i8>*
-  %res1 = load <16 x i8>* %addr2_v16xI8, align 1
-  %res2 = load <16 x i8>* %addr_v16xI8, align 1
-  %res3 = load <16 x i8>* %addr3_v16xI8, align 1
+  %res1 = load <16 x i8>, <16 x i8>* %addr2_v16xI8, align 1
+  %res2 = load <16 x i8>, <16 x i8>* %addr_v16xI8, align 1
+  %res3 = load <16 x i8>, <16 x i8>* %addr3_v16xI8, align 1
   %res12 = add <16 x i8> %res1, %res2
   %res123 = add <16 x i8> %res12, %res3
   ret <16 x i8> %res123
 }
 ; CHECK-LABEL: load_v16xI8
 ; CHECK: 0f 10 0{{.*}} movups xmm0,XMMWORD PTR [e{{.*}}]
 
 ; Test segment override prefix. This happens w/ nacl.read.tp.
 declare i8* @llvm.nacl.read.tp()
 
 ; Also test more address complex operands via address-mode-optimization.
 define i32 @test_nacl_read_tp_more_addressing() {
 entry:
   %ptr = call i8* @llvm.nacl.read.tp()
   %__1 = ptrtoint i8* %ptr to i32
   %x = add i32 %__1, %__1
   %__3 = inttoptr i32 %x to i32*
-  %v = load i32* %__3, align 1
+  %v = load i32, i32* %__3, align 1
   %v_add = add i32 %v, 1
 
   %ptr2 = call i8* @llvm.nacl.read.tp()
   %__6 = ptrtoint i8* %ptr2 to i32
   %y = add i32 %__6, -128
   %__8 = inttoptr i32 %y to i32*
   %v_add2 = add i32 %v, 4
   store i32 %v_add2, i32* %__8, align 1
 
   %z = add i32 %__6, 256
@@ skipping 135 matching lines @@
 three:
   %res3 = extractelement <8 x i16> %vec4, i32 7
   %res3_ext = zext i16 %res3 to i32
   ret i32 %res3_ext
 }
 ; CHECK-LABEL: test_pextrw
 ; CHECK-DAG: 66 0f c5 c0 00 pextrw eax,xmm0
 ; CHECK-DAG: 66 0f c5 c1 02 pextrw eax,xmm1
 ; CHECK-DAG: 66 0f c5 c2 05 pextrw eax,xmm2
 ; CHECK-DAG: 66 0f c5 c3 07 pextrw eax,xmm3