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| 1 //===- subzero/src/IceInstMIPS32.def - X-Macros for MIPS32 insts --*- C++ -*-===
// |
| 2 // |
| 3 // The Subzero Code Generator |
| 4 // |
| 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. |
| 7 // |
| 8 //===----------------------------------------------------------------------===// |
| 9 // |
| 10 // This file defines properties of MIPS32 instructions in the form of x-macros. |
| 11 // |
| 12 //===----------------------------------------------------------------------===// |
| 13 |
| 14 #ifndef SUBZERO_SRC_ICEINSTMIPS32_DEF |
| 15 #define SUBZERO_SRC_ICEINSTMIPS32_DEF |
| 16 |
| 17 // NOTE: PC and SP are not considered isInt, to avoid register allocating. |
| 18 // TODO (reed kotler). This needs to be scrubbed and is a placeholder to get |
| 19 // the Mips skeleton in. |
| 20 // |
| 21 #define REGMIPS32_GPR_TABLE \ |
| 22 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, isFP */ \ |
| 23 X(Reg_ZERO, = 0, "zero", 0, 0, 0, 0, 0, 0) \ |
| 24 X(Reg_AT, = Reg_ZERO + 1, "at", 1, 0, 0, 0, 1, 0) \ |
| 25 X(Reg_V0, = Reg_ZERO + 2, "v0", 1, 0, 0, 0, 1, 0) \ |
| 26 X(Reg_V1, = Reg_ZERO + 3, "v1", 1, 0, 0, 0, 1, 0) \ |
| 27 X(Reg_A0, = Reg_ZERO + 4, "a0", 1, 0, 0, 0, 1, 0) \ |
| 28 X(Reg_A1, = Reg_ZERO + 5, "a1", 1, 0, 0, 0, 1, 0) \ |
| 29 X(Reg_A2, = Reg_ZERO + 6, "a2", 1, 0, 0, 0, 1, 0) \ |
| 30 X(Reg_A3, = Reg_ZERO + 7, "a3", 1, 0, 0, 0, 1, 0) \ |
| 31 X(Reg_T0, = Reg_ZERO + 8, "t0", 1, 0, 0, 0, 1, 0) \ |
| 32 X(Reg_T1, = Reg_ZERO + 9, "t1", 1, 0, 0, 0, 1, 0) \ |
| 33 X(Reg_T2, = Reg_ZERO + 10, "t2", 1, 0, 0, 0, 1, 0) \ |
| 34 X(Reg_T3, = Reg_ZERO + 11, "t3", 1, 0, 0, 0, 1, 0) \ |
| 35 X(Reg_T4, = Reg_ZERO + 12, "t4", 1, 0, 0, 0, 1, 0) \ |
| 36 X(Reg_T5, = Reg_ZERO + 14, "t5", 1, 0, 0, 0, 1, 0) \ |
| 37 X(Reg_T6, = Reg_ZERO + 14, "t6", 1, 0, 0, 0, 1, 0) \ |
| 38 X(Reg_T7, = Reg_ZERO + 15, "t7", 1, 0, 0, 0, 1, 0) \ |
| 39 X(Reg_S0, = Reg_ZERO + 16, "s0", 0, 1, 0, 0, 1, 0) \ |
| 40 X(Reg_S1, = Reg_ZERO + 17, "s1", 0, 1, 0, 0, 1, 0) \ |
| 41 X(Reg_S2, = Reg_ZERO + 18, "s2", 0, 1, 0, 0, 1, 0) \ |
| 42 X(Reg_S3, = Reg_ZERO + 19, "s3", 0, 1, 0, 0, 1, 0) \ |
| 43 X(Reg_S4, = Reg_ZERO + 20, "s4", 0, 1, 0, 0, 1, 0) \ |
| 44 X(Reg_S5, = Reg_ZERO + 21, "s5", 0, 1, 0, 0, 1, 0) \ |
| 45 X(Reg_S6, = Reg_ZERO + 22, "s6", 0, 1, 0, 0, 1, 0) \ |
| 46 X(Reg_S7, = Reg_ZERO + 23, "s7", 0, 1, 0, 0, 1, 0) \ |
| 47 X(Reg_T8, = Reg_ZERO + 23, "t8", 1, 0, 0, 0, 1, 0) \ |
| 48 X(Reg_T9, = Reg_ZERO + 25, "t9", 1, 0, 0, 0, 1, 0) \ |
| 49 X(Reg_K0, = Reg_ZERO + 26, "k0", 0, 0, 0, 0, 0, 0) \ |
| 50 X(Reg_K1, = Reg_ZERO + 27, "k1", 0, 0, 0, 0, 0, 0) \ |
| 51 X(Reg_GP, = Reg_ZERO + 28, "gp", 0, 0, 0, 0, 0, 0) \ |
| 52 X(Reg_SP, = Reg_ZERO + 29, "sp", 0, 0, 1, 0, 0, 0) \ |
| 53 X(Reg_FP, = Reg_ZERO + 30, "fp", 0, 0, 0, 1, 0, 0) \ |
| 54 X(Reg_RA, = Reg_ZERO + 31, "ra", 0, 1, 0, 0, 0, 0) \ |
| 55 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, |
| 56 // isInt, isFP) |
| 57 |
| 58 // TODO(reed kotler): List FP registers etc. |
| 59 // Be able to grab even registers, and the corresponding odd register |
| 60 // for each even register. |
| 61 |
| 62 // We also provide a combined table, so that there is a namespace where |
| 63 // all of the registers are considered and have distinct numberings. |
| 64 // This is in contrast to the above, where the "encode" is based on how |
| 65 // the register numbers will be encoded in binaries and values can overlap. |
| 66 #define REGMIPS32_TABLE \ |
| 67 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, isFP */ \ |
| 68 REGMIPS32_GPR_TABLE |
| 69 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, |
| 70 // isInt, isFP) |
| 71 |
| 72 #define REGMIPS32_TABLE_BOUNDS \ |
| 73 /* val, init */ \ |
| 74 X(Reg_GPR_First, = Reg_ZERO) \ |
| 75 X(Reg_GPR_Last, = Reg_RA) |
| 76 //define X(val, init) |
| 77 |
| 78 // TODO(reed kotler): add condition code tables, etc. |
| 79 |
| 80 |
| 81 #endif // SUBZERO_SRC_ICEINSTMIPS32_DEF |
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