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1 ; This file checks that Subzero generates code in accordance with the | 1 ; This file checks that Subzero generates code in accordance with the |
2 ; calling convention for integers. | 2 ; calling convention for integers. |
3 | 3 |
4 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ | 4 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ |
5 ; RUN: --target x8632 -i %s --args -O2 \ | 5 ; RUN: --target x8632 -i %s --args -O2 \ |
6 ; RUN: | %if --need=target_X8632 --command FileCheck %s | 6 ; RUN: | %if --need=target_X8632 --command FileCheck %s |
7 | 7 |
8 ; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented) | 8 ; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented) |
9 ; once enough infrastructure is in. Also, switch to --filetype=obj | 9 ; once enough infrastructure is in. Also, switch to --filetype=obj |
10 ; when possible. | 10 ; when possible. |
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66 | 66 |
67 | 67 |
68 define i32 @test_returning32_arg4(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i3
2 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) { | 68 define i32 @test_returning32_arg4(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i3
2 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) { |
69 entry: | 69 entry: |
70 ret i32 %arg4 | 70 ret i32 %arg4 |
71 } | 71 } |
72 ; CHECK-LABEL: test_returning32_arg4 | 72 ; CHECK-LABEL: test_returning32_arg4 |
73 ; CHECK-NEXT: mov eax,{{.*}} [esp+0x14] | 73 ; CHECK-NEXT: mov eax,{{.*}} [esp+0x14] |
74 ; CHECK-NEXT: ret | 74 ; CHECK-NEXT: ret |
75 ; ARM32-LABEL: test_returning32_arg4 | 75 ; ARM32-LABEL: test_returning32_arg4 |
76 ; TODO(jvoung): Toggle this on, once addProlog is done. | 76 ; ARM32-NEXT: ldr r0, [sp] |
77 ; TODOARM32-NEXT: ldr r0, [sp] | |
78 ; ARM32-NEXT: bx lr | 77 ; ARM32-NEXT: bx lr |
79 | 78 |
80 | 79 |
81 define i32 @test_returning32_arg5(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i3
2 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) { | 80 define i32 @test_returning32_arg5(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i3
2 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) { |
82 entry: | 81 entry: |
83 ret i32 %arg5 | 82 ret i32 %arg5 |
84 } | 83 } |
85 ; CHECK-LABEL: test_returning32_arg5 | 84 ; CHECK-LABEL: test_returning32_arg5 |
86 ; CHECK-NEXT: mov eax,{{.*}} [esp+0x18] | 85 ; CHECK-NEXT: mov eax,{{.*}} [esp+0x18] |
87 ; CHECK-NEXT: ret | 86 ; CHECK-NEXT: ret |
88 ; ARM32-LABEL: test_returning32_arg5 | 87 ; ARM32-LABEL: test_returning32_arg5 |
89 ; TODO(jvoung): Toggle this on, once addProlog is done. | 88 ; ARM32-NEXT: ldr r0, [sp, #4] |
90 ; TODOARM32-NEXT: ldr r0, [sp, #4] | |
91 ; ARM32-NEXT: bx lr | 89 ; ARM32-NEXT: bx lr |
92 | 90 |
93 ; i64 | 91 ; i64 |
94 | 92 |
95 define i64 @test_returning64_arg0(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) { | 93 define i64 @test_returning64_arg0(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) { |
96 entry: | 94 entry: |
97 ret i64 %arg0 | 95 ret i64 %arg0 |
98 } | 96 } |
99 ; CHECK-LABEL: test_returning64_arg0 | 97 ; CHECK-LABEL: test_returning64_arg0 |
100 ; CHECK-NEXT: mov {{.*}} [esp+0x4] | 98 ; CHECK-NEXT: mov {{.*}} [esp+0x4] |
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119 define i64 @test_returning64_arg2(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) { | 117 define i64 @test_returning64_arg2(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) { |
120 entry: | 118 entry: |
121 ret i64 %arg2 | 119 ret i64 %arg2 |
122 } | 120 } |
123 ; CHECK-LABEL: test_returning64_arg2 | 121 ; CHECK-LABEL: test_returning64_arg2 |
124 ; CHECK-NEXT: mov {{.*}} [esp+0x14] | 122 ; CHECK-NEXT: mov {{.*}} [esp+0x14] |
125 ; CHECK-NEXT: mov {{.*}} [esp+0x18] | 123 ; CHECK-NEXT: mov {{.*}} [esp+0x18] |
126 ; CHECK: ret | 124 ; CHECK: ret |
127 ; ARM32-LABEL: test_returning64_arg2 | 125 ; ARM32-LABEL: test_returning64_arg2 |
128 ; This could have been a ldm sp, {r0, r1}, but we don't do the ldm optimization. | 126 ; This could have been a ldm sp, {r0, r1}, but we don't do the ldm optimization. |
129 ; TODO(jvoung): enable this once addProlog is done. | 127 ; ARM32-NEXT: ldr r0, [sp] |
130 ; TODOARM32-NEXT: ldr r0, [sp] | 128 ; ARM32-NEXT: ldr r1, [sp, #4] |
131 ; TODOARM32-NEXT: ldr r1, [sp, #4] | |
132 ; ARM32-NEXT: bx lr | 129 ; ARM32-NEXT: bx lr |
133 | 130 |
134 define i64 @test_returning64_arg3(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) { | 131 define i64 @test_returning64_arg3(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) { |
135 entry: | 132 entry: |
136 ret i64 %arg3 | 133 ret i64 %arg3 |
137 } | 134 } |
138 ; CHECK-LABEL: test_returning64_arg3 | 135 ; CHECK-LABEL: test_returning64_arg3 |
139 ; CHECK-NEXT: mov {{.*}} [esp+0x1c] | 136 ; CHECK-NEXT: mov {{.*}} [esp+0x1c] |
140 ; CHECK-NEXT: mov {{.*}} [esp+0x20] | 137 ; CHECK-NEXT: mov {{.*}} [esp+0x20] |
141 ; CHECK: ret | 138 ; CHECK: ret |
142 ; ARM32-LABEL: test_returning64_arg3 | 139 ; ARM32-LABEL: test_returning64_arg3 |
143 ; TODO(jvoung): enable this once addProlog is done. | 140 ; ARM32-NEXT: ldr r0, [sp, #8] |
144 ; TODOARM32-NEXT: ldr r0, [sp, #8] | 141 ; ARM32-NEXT: ldr r1, [sp, #12] |
145 ; TODOARM32-NEXT: ldr r1, [sp, #12] | |
146 ; ARM32-NEXT: bx lr | 142 ; ARM32-NEXT: bx lr |
147 | 143 |
148 | 144 |
149 ; Test that on ARM, the i64 arguments start with an even register. | 145 ; Test that on ARM, the i64 arguments start with an even register. |
150 | 146 |
151 define i64 @test_returning64_even_arg1(i32 %arg0, i64 %arg1, i64 %arg2) { | 147 define i64 @test_returning64_even_arg1(i32 %arg0, i64 %arg1, i64 %arg2) { |
152 entry: | 148 entry: |
153 ret i64 %arg1 | 149 ret i64 %arg1 |
154 } | 150 } |
155 ; Not padded out x86-32. | 151 ; Not padded out x86-32. |
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178 define i64 @test_returning64_even_arg2(i64 %arg0, i32 %arg1, i64 %arg2) { | 174 define i64 @test_returning64_even_arg2(i64 %arg0, i32 %arg1, i64 %arg2) { |
179 entry: | 175 entry: |
180 ret i64 %arg2 | 176 ret i64 %arg2 |
181 } | 177 } |
182 ; Not padded out on x86-32. | 178 ; Not padded out on x86-32. |
183 ; CHECK-LABEL: test_returning64_even_arg2 | 179 ; CHECK-LABEL: test_returning64_even_arg2 |
184 ; CHECK-NEXT: mov {{.*}} [esp+0x10] | 180 ; CHECK-NEXT: mov {{.*}} [esp+0x10] |
185 ; CHECK-NEXT: mov {{.*}} [esp+0x14] | 181 ; CHECK-NEXT: mov {{.*}} [esp+0x14] |
186 ; CHECK: ret | 182 ; CHECK: ret |
187 ; ARM32-LABEL: test_returning64_even_arg2 | 183 ; ARM32-LABEL: test_returning64_even_arg2 |
188 ; TODO(jvoung): enable this once addProlog is done. | 184 ; ARM32-NEXT: ldr r0, [sp] |
189 ; TODOARM32-NEXT: ldr r0, [sp] | 185 ; ARM32-NEXT: ldr r1, [sp, #4] |
190 ; TODOARM32-NEXT: ldr r1, [sp, #4] | |
191 ; ARM32-NEXT: bx lr | 186 ; ARM32-NEXT: bx lr |
192 | 187 |
193 define i64 @test_returning64_even_arg2b(i64 %arg0, i32 %arg1, i32 %arg1b, i64 %a
rg2) { | 188 define i64 @test_returning64_even_arg2b(i64 %arg0, i32 %arg1, i32 %arg1b, i64 %a
rg2) { |
194 entry: | 189 entry: |
195 ret i64 %arg2 | 190 ret i64 %arg2 |
196 } | 191 } |
197 ; CHECK-LABEL: test_returning64_even_arg2b | 192 ; CHECK-LABEL: test_returning64_even_arg2b |
198 ; CHECK-NEXT: mov {{.*}} [esp+0x14] | 193 ; CHECK-NEXT: mov {{.*}} [esp+0x14] |
199 ; CHECK-NEXT: mov {{.*}} [esp+0x18] | 194 ; CHECK-NEXT: mov {{.*}} [esp+0x18] |
200 ; CHECK: ret | 195 ; CHECK: ret |
201 ; ARM32-LABEL: test_returning64_even_arg2b | 196 ; ARM32-LABEL: test_returning64_even_arg2b |
202 ; TODO(jvoung): enable this once addProlog is done. | 197 ; ARM32-NEXT: ldr r0, [sp] |
203 ; TODOARM32-NEXT: ldr r0, [sp] | 198 ; ARM32-NEXT: ldr r1, [sp, #4] |
204 ; TODOARM32-NEXT: ldr r1, [sp, #4] | |
205 ; ARM32-NEXT: bx lr | 199 ; ARM32-NEXT: bx lr |
206 | 200 |
207 define i32 @test_returning32_even_arg2(i64 %arg0, i32 %arg1, i32 %arg2) { | 201 define i32 @test_returning32_even_arg2(i64 %arg0, i32 %arg1, i32 %arg2) { |
208 entry: | 202 entry: |
209 ret i32 %arg2 | 203 ret i32 %arg2 |
210 } | 204 } |
211 ; CHECK-LABEL: test_returning32_even_arg2 | 205 ; CHECK-LABEL: test_returning32_even_arg2 |
212 ; CHECK-NEXT: mov {{.*}} [esp+0x10] | 206 ; CHECK-NEXT: mov {{.*}} [esp+0x10] |
213 ; CHECK-NEXT: ret | 207 ; CHECK-NEXT: ret |
214 ; ARM32-LABEL: test_returning32_even_arg2 | 208 ; ARM32-LABEL: test_returning32_even_arg2 |
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229 ; The i64 won't fit in a pair of register, and consumes the last register so a | 223 ; The i64 won't fit in a pair of register, and consumes the last register so a |
230 ; following i32 can't use that free register. | 224 ; following i32 can't use that free register. |
231 define i32 @test_returning32_even_arg4(i32 %arg0, i32 %arg1, i32 %arg2, i64 %arg
3, i32 %arg4) { | 225 define i32 @test_returning32_even_arg4(i32 %arg0, i32 %arg1, i32 %arg2, i64 %arg
3, i32 %arg4) { |
232 entry: | 226 entry: |
233 ret i32 %arg4 | 227 ret i32 %arg4 |
234 } | 228 } |
235 ; CHECK-LABEL: test_returning32_even_arg4 | 229 ; CHECK-LABEL: test_returning32_even_arg4 |
236 ; CHECK-NEXT: mov {{.*}} [esp+0x18] | 230 ; CHECK-NEXT: mov {{.*}} [esp+0x18] |
237 ; CHECK-NEXT: ret | 231 ; CHECK-NEXT: ret |
238 ; ARM32-LABEL: test_returning32_even_arg4 | 232 ; ARM32-LABEL: test_returning32_even_arg4 |
239 ; TODO(jvoung): enable this once addProlog is done. | 233 ; ARM32-NEXT: ldr r0, [sp, #8] |
240 ; TODOARM32-NEXT: ldr r0, [sp, #8] | |
241 ; ARM32-NEXT: bx lr | 234 ; ARM32-NEXT: bx lr |
242 | 235 |
243 ; Test interleaving float/double and integer (different register streams on ARM)
. | 236 ; Test interleaving float/double and integer (different register streams on ARM)
. |
244 ; TODO(jvoung): Test once the S/D/Q regs are modeled. | 237 ; TODO(jvoung): Test once the S/D/Q regs are modeled. |
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