Subzero ARM: addProlog/addEpilogue -- share some code with x86.

tests_lit/llvm2ice_tests/alloc.ll

 ; This is a basic test of the alloca instruction.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
@@ skipping 109 matching lines @@
 
 define void @variable_n_align_32(i32 %n) {
 entry:
   %array = alloca i8, i32 %n, align 32
   %__2 = ptrtoint i8* %array to i32
   call void @f2(i32 %__2)
   ret void
 }
 ; In -O2, the order of the CHECK-DAG lines in the output is switched.
 ; CHECK-LABEL: variable_n_align_32
+; CHECK:      push    ebp
+; CHECK:      mov     ebp,esp
 ; CHECK-DAG:  and     esp,0xffffffe0
 ; CHECK-DAG:  mov     eax,DWORD PTR [ebp+0x8]
 ; CHECK:      add     eax,0x1f
 ; CHECK:      and     eax,0xffffffe0
 ; CHECK:      sub     esp,eax
 ; CHECK:      sub     esp,0x10
 ; CHECK:      mov     DWORD PTR [esp],eax
 ; CHECK:      call {{.*}} R_{{.*}}    f2
+; CHECK:      mov     esp,ebp
+; CHECK:      pop     ebp
 
 ; ARM32-LABEL: variable_n_align_32
+; ARM32:      push {fp, lr}
+; ARM32:      mov fp, sp
 ; ARM32:      bic sp, sp, #31
 ; ARM32:      add r0, r0, #31
 ; ARM32:      bic r0, r0, #31
 ; ARM32:      sub sp, sp, r0
 ; ARM32:      bl {{.*}} R_{{.*}}    f2
+; ARM32:      mov sp, fp
+; ARM32:      pop {fp, lr}
 
 ; Test alloca with default (0) alignment.
 define void @align0(i32 %n) {
 entry:
   %array = alloca i8, i32 %n
   %__2 = ptrtoint i8* %array to i32
   call void @f2(i32 %__2)
   ret void
 }
 ; CHECK-LABEL: align0
@@ skipping 47 matching lines @@
 ; CHECK: add [[REG:.*]],0x1fffffff
 ; CHECK: and [[REG]],0xe0000000
 ; CHECK: sub esp,[[REG]]
 
 ; ARM32-LABEL: align512MB
 ; ARM32: and sp, sp, #-536870912 ; 0xe0000000
 ; ARM32: mvn [[REG:.*]], #-536870912 ; 0xe0000000
 ; ARM32: add r0, r0, [[REG]]
 ; ARM32: and r0, r0, #-536870912 ; 0xe0000000
 ; ARM32: sub sp, sp, r0