Subzero ARM: addProlog/addEpilogue -- share some code with x86.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the InstARM32 and OperandARM32 classes and
@@ skipping 95 matching lines @@
         OperandARM32Mem(Func, Ty, Base, Index, ShiftOp, ShiftAmt, Mode);
   }
   Variable *getBase() const { return Base; }
   ConstantInteger32 *getOffset() const { return ImmOffset; }
   Variable *getIndex() const { return Index; }
   ShiftKind getShiftOp() const { return ShiftOp; }
   uint16_t getShiftAmt() const { return ShiftAmt; }
   AddrMode getAddrMode() const { return Mode; }
 
   bool isRegReg() const { return Index != nullptr; }
-  bool isNegAddrMode() const { return Mode >= NegOffset; }
+  bool isNegAddrMode() const {
+    // Positive address modes have the "U" bit set, and negative modes don't.
+    static_assert((PreIndex & (4 << 21)) != 0,
+                  "Positive addr modes should have U bit set.");
+    static_assert((NegPreIndex & (4 << 21)) == 0,
+                  "Negative addr modes should have U bit clear.");
+    return (Mode & (4 << 21)) == 0;
+  }
 
   void emit(const Cfg *Func) const override;
   using OperandARM32::dump;
   void dump(const Cfg *Func, Ostream &Str) const override;
 
   static bool classof(const Operand *Operand) {
     return Operand->getKind() == static_cast<OperandKind>(kMem);
   }
 
   // Return true if a load/store instruction for an element of type Ty
@@ skipping 132 matching lines @@
     Eor,
     Ldr,
     Lsl,
     Mla,
     Mov,
     Movt,
     Movw,
     Mul,
     Mvn,
     Orr,
+    Pop,
+    Push,
     Ret,
     Sbc,
     Sub,
     Umull
   };
 
   static const char *getWidthString(Type Ty);
   static CondARM32::Cond getOppositeCondition(CondARM32::Cond Cond);
 
   void dump(const Cfg *Func) const override;
@@ skipping 396 matching lines @@
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Mla); }
 
 private:
   InstARM32Mla(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1,
                Variable *Acc, CondARM32::Cond Predicate);
   ~InstARM32Mla() override {}
 };
 
+// Pop into a list of GPRs. Technically this can be predicated, but we don't
+// need that functionality.
+class InstARM32Pop : public InstARM32 {
+  InstARM32Pop() = delete;
+  InstARM32Pop(const InstARM32Pop &) = delete;
+  InstARM32Pop &operator=(const InstARM32Pop &) = delete;
+
+public:
+  static InstARM32Pop *create(Cfg *Func, const VarList &Dests) {
+    return new (Func->allocate<InstARM32Pop>()) InstARM32Pop(Func, Dests);
+  }
+  void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
+  void dump(const Cfg *Func) const override;
+  static bool classof(const Inst *Inst) { return isClassof(Inst, Pop); }
+
+private:
+  InstARM32Pop(Cfg *Func, const VarList &Dests);
+  ~InstARM32Pop() override {}
+  VarList Dests;
+};
+
+// Push a list of GPRs. Technically this can be predicated, but we don't
+// need that functionality.
+class InstARM32Push : public InstARM32 {
+  InstARM32Push() = delete;
+  InstARM32Push(const InstARM32Push &) = delete;
+  InstARM32Push &operator=(const InstARM32Push &) = delete;
+
+public:
+  static InstARM32Push *create(Cfg *Func, const VarList &Srcs) {
+    return new (Func->allocate<InstARM32Push>()) InstARM32Push(Func, Srcs);
+  }
+  void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
+  void dump(const Cfg *Func) const override;
+  static bool classof(const Inst *Inst) { return isClassof(Inst, Push); }
+
+private:
+  InstARM32Push(Cfg *Func, const VarList &Srcs);
+  ~InstARM32Push() override {}
+};
+
 // Ret pseudo-instruction.  This is actually a "bx" instruction with
 // an "lr" register operand, but epilogue lowering will search for a Ret
 // instead of a generic "bx". This instruction also takes a Source
 // operand (for non-void returning functions) for liveness analysis, though
 // a FakeUse before the ret would do just as well.
 //
 // NOTE: Even though "bx" can be predicated, for now leave out the predication
 // since it's not yet known to be useful for Ret. That may complicate finding
 // the terminator instruction if it's not guaranteed to be executed.
 class InstARM32Ret : public InstARM32 {
@@ skipping 45 matching lines @@
 // Declare partial template specializations of emit() methods that
 // already have default implementations.  Without this, there is the
 // possibility of ODR violations and link errors.
 
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H