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Side by Side Diff: src/IceInstARM32.cpp

Issue 1159013002: Subzero ARM: addProlog/addEpilogue -- share some code with x86. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: typo Created 5 years, 6 months ago
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1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the InstARM32 and OperandARM32 classes, 10 // This file implements the InstARM32 and OperandARM32 classes,
(...skipping 242 matching lines...) Expand 10 before | Expand all | Expand 10 after
253 253
254 InstARM32Mla::InstARM32Mla(Cfg *Func, Variable *Dest, Variable *Src0, 254 InstARM32Mla::InstARM32Mla(Cfg *Func, Variable *Dest, Variable *Src0,
255 Variable *Src1, Variable *Acc, 255 Variable *Src1, Variable *Acc,
256 CondARM32::Cond Predicate) 256 CondARM32::Cond Predicate)
257 : InstARM32Pred(Func, InstARM32::Mla, 3, Dest, Predicate) { 257 : InstARM32Pred(Func, InstARM32::Mla, 3, Dest, Predicate) {
258 addSource(Src0); 258 addSource(Src0);
259 addSource(Src1); 259 addSource(Src1);
260 addSource(Acc); 260 addSource(Acc);
261 } 261 }
262 262
263 InstARM32Pop::InstARM32Pop(Cfg *Func, const VarList &Dests)
264 : InstARM32(Func, InstARM32::Pop, 0, nullptr), Dests(Dests) {
265 // Track modifications to Dests separately via FakeDefs.
266 // Also, a pop instruction affects the stack pointer and so it should not
267 // be allowed to be automatically dead-code eliminated. This is automatic
268 // since we leave the Dest as nullptr.
269 }
270
271 InstARM32Push::InstARM32Push(Cfg *Func, const VarList &Srcs)
272 : InstARM32(Func, InstARM32::Push, Srcs.size(), nullptr) {
273 for (Variable *Source : Srcs)
274 addSource(Source);
275 }
276
263 InstARM32Ret::InstARM32Ret(Cfg *Func, Variable *LR, Variable *Source) 277 InstARM32Ret::InstARM32Ret(Cfg *Func, Variable *LR, Variable *Source)
264 : InstARM32(Func, InstARM32::Ret, Source ? 2 : 1, nullptr) { 278 : InstARM32(Func, InstARM32::Ret, Source ? 2 : 1, nullptr) {
265 addSource(LR); 279 addSource(LR);
266 if (Source) 280 if (Source)
267 addSource(Source); 281 addSource(Source);
268 } 282 }
269 283
270 InstARM32Umull::InstARM32Umull(Cfg *Func, Variable *DestLo, Variable *DestHi, 284 InstARM32Umull::InstARM32Umull(Cfg *Func, Variable *DestLo, Variable *DestHi,
271 Variable *Src0, Variable *Src1, 285 Variable *Src0, Variable *Src1,
272 CondARM32::Cond Predicate) 286 CondARM32::Cond Predicate)
(...skipping 274 matching lines...) Expand 10 before | Expand all | Expand 10 after
547 Dest->emit(Func); 561 Dest->emit(Func);
548 Str << ", "; 562 Str << ", ";
549 if (auto CR = llvm::dyn_cast<ConstantRelocatable>(Src1)) { 563 if (auto CR = llvm::dyn_cast<ConstantRelocatable>(Src1)) {
550 Str << "#:upper16:"; 564 Str << "#:upper16:";
551 CR->emitWithoutPrefix(Func->getTarget()); 565 CR->emitWithoutPrefix(Func->getTarget());
552 } else { 566 } else {
553 Src1->emit(Func); 567 Src1->emit(Func);
554 } 568 }
555 } 569 }
556 570
571 void InstARM32Pop::emit(const Cfg *Func) const {
572 if (!ALLOW_DUMP)
573 return;
574 assert(Dests.size() > 0);
575 Ostream &Str = Func->getContext()->getStrEmit();
576 Str << "\t"
577 << "pop"
578 << "\t{";
579 for (SizeT I = 0; I < Dests.size(); ++I) {
580 if (I > 0)
581 Str << ", ";
582 Dests[I]->emit(Func);
583 }
584 Str << "}";
585 }
586
587 void InstARM32Pop::emitIAS(const Cfg *Func) const {
588 (void)Func;
589 llvm_unreachable("Not yet implemented");
590 }
591
592 void InstARM32Pop::dump(const Cfg *Func) const {
593 if (!ALLOW_DUMP)
594 return;
595 Ostream &Str = Func->getContext()->getStrDump();
596 Str << "pop"
597 << " ";
598 for (SizeT I = 0; I < Dests.size(); ++I) {
599 if (I > 0)
600 Str << ", ";
601 Dests[I]->dump(Func);
602 }
603 }
604
605 void InstARM32Push::emit(const Cfg *Func) const {
606 if (!ALLOW_DUMP)
607 return;
608 assert(getSrcSize() > 0);
609 Ostream &Str = Func->getContext()->getStrEmit();
610 Str << "\t"
611 << "push"
612 << "\t{";
613 emitSources(Func);
614 Str << "}";
615 }
616
617 void InstARM32Push::emitIAS(const Cfg *Func) const {
618 (void)Func;
619 llvm_unreachable("Not yet implemented");
620 }
621
622 void InstARM32Push::dump(const Cfg *Func) const {
623 if (!ALLOW_DUMP)
624 return;
625 Ostream &Str = Func->getContext()->getStrDump();
626 Str << "push"
627 << " ";
628 dumpSources(Func);
629 }
630
557 void InstARM32Ret::emit(const Cfg *Func) const { 631 void InstARM32Ret::emit(const Cfg *Func) const {
558 if (!ALLOW_DUMP) 632 if (!ALLOW_DUMP)
559 return; 633 return;
560 assert(getSrcSize() > 0); 634 assert(getSrcSize() > 0);
561 Variable *LR = llvm::cast<Variable>(getSrc(0)); 635 Variable *LR = llvm::cast<Variable>(getSrc(0));
562 assert(LR->hasReg()); 636 assert(LR->hasReg());
563 assert(LR->getRegNum() == RegARM32::Reg_lr); 637 assert(LR->getRegNum() == RegARM32::Reg_lr);
564 Ostream &Str = Func->getContext()->getStrEmit(); 638 Ostream &Str = Func->getContext()->getStrEmit();
565 Str << "\t" 639 Str << "\t"
566 << "bx" 640 << "bx"
(...skipping 109 matching lines...) Expand 10 before | Expand all | Expand 10 after
676 getIndex()->dump(Func); 750 getIndex()->dump(Func);
677 else 751 else
678 getIndex()->dump(Str); 752 getIndex()->dump(Str);
679 if (getShiftOp() != kNoShift) { 753 if (getShiftOp() != kNoShift) {
680 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " #" 754 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " #"
681 << getShiftAmt(); 755 << getShiftAmt();
682 } 756 }
683 } else { 757 } else {
684 getOffset()->dump(Func, Str); 758 getOffset()->dump(Func, Str);
685 } 759 }
686 Str << "] AddrMode==" << getAddrMode() << "\n"; 760 Str << "] AddrMode==" << getAddrMode();
687 } 761 }
688 762
689 void OperandARM32FlexImm::emit(const Cfg *Func) const { 763 void OperandARM32FlexImm::emit(const Cfg *Func) const {
690 if (!ALLOW_DUMP) 764 if (!ALLOW_DUMP)
691 return; 765 return;
692 Ostream &Str = Func->getContext()->getStrEmit(); 766 Ostream &Str = Func->getContext()->getStrEmit();
693 uint32_t Imm = getImm(); 767 uint32_t Imm = getImm();
694 uint32_t RotateAmt = getRotateAmt(); 768 uint32_t RotateAmt = getRotateAmt();
695 Str << "#" << Utils::rotateRight32(Imm, 2 * RotateAmt); 769 Str << "#" << Utils::rotateRight32(Imm, 2 * RotateAmt);
696 } 770 }
(...skipping 28 matching lines...) Expand all
725 if (getShiftOp() != kNoShift) { 799 if (getShiftOp() != kNoShift) {
726 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " "; 800 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
727 if (Func) 801 if (Func)
728 getShiftAmt()->dump(Func); 802 getShiftAmt()->dump(Func);
729 else 803 else
730 getShiftAmt()->dump(Str); 804 getShiftAmt()->dump(Str);
731 } 805 }
732 } 806 }
733 807
734 } // end of namespace Ice 808 } // end of namespace Ice
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