Subzero ARM: addProlog/addEpilogue -- share some code with x86.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstARM32 and OperandARM32 classes,
@@ skipping 242 matching lines @@
 
 InstARM32Mla::InstARM32Mla(Cfg *Func, Variable *Dest, Variable *Src0,
                            Variable *Src1, Variable *Acc,
                            CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Mla, 3, Dest, Predicate) {
   addSource(Src0);
   addSource(Src1);
   addSource(Acc);
 }
 
+InstARM32Pop::InstARM32Pop(Cfg *Func, const VarList &Dests)
+    : InstARM32(Func, InstARM32::Pop, 0, Dests[0]), Dests(Dests) {
+  // We only track the first Dest directly. Other Dests should be

[Jim Stichnoth, 2015/05/30 16:58:54]

I think we should consider treating the Dests values more uniformly - leave
InstARM32Pop::Dest=nullptr, omit the HasSideEffects=true assignment, and add
FakeDef instructions for each Dests[] variable including Dest[0].

[jvoung (off chromium), 2015/06/01 18:00:23]

Yeah that seems cleaner, and it's already storing the whole list locally w/
"Dests(Dests)". Done.

+  // modeled with a FakeDef.
+  // A pop instruction affects the stack pointer and so it should not
+  // be allowed to be automatically dead-code eliminated.  (The
+  // corresponding push instruction doesn't need this treatment
+  // because it has no dest variable and therefore won't be dead-code
+  // eliminated.)  This is needed for late-stage liveness analysis
+  // (e.g. asm-verbose mode).
+  HasSideEffects = true;
+}
+
+InstARM32Push::InstARM32Push(Cfg *Func, const VarList &Srcs)
+    : InstARM32(Func, InstARM32::Push, Srcs.size(), nullptr) {
+  for (Variable *Source : Srcs)
+    addSource(Source);
+}
+
 InstARM32Ret::InstARM32Ret(Cfg *Func, Variable *LR, Variable *Source)
     : InstARM32(Func, InstARM32::Ret, Source ? 2 : 1, nullptr) {
   addSource(LR);
   if (Source)
     addSource(Source);
 }
 
 InstARM32Umull::InstARM32Umull(Cfg *Func, Variable *DestLo, Variable *DestHi,
                                Variable *Src0, Variable *Src1,
                                CondARM32::Cond Predicate)
@@ skipping 274 matching lines @@
   Dest->emit(Func);
   Str << ", ";
   if (auto CR = llvm::dyn_cast<ConstantRelocatable>(Src1)) {
     Str << "#:upper16:";
     CR->emitWithoutPrefix(Func->getTarget());
   } else {
     Src1->emit(Func);
   }
 }
 
+void InstARM32Pop::emit(const Cfg *Func) const {
+  if (!ALLOW_DUMP)
+    return;
+  assert(Dests.size() > 0);
+  Ostream &Str = Func->getContext()->getStrEmit();
+  Str << "\t"
+      << "pop"
+      << "\t{";
+  for (SizeT I = 0; I < Dests.size(); ++I) {
+    if (I > 0)
+      Str << ", ";
+    Dests[I]->emit(Func);
+  }
+  Str << "}";
+}
+
+void InstARM32Pop::emitIAS(const Cfg *Func) const {
+  (void)Func;
+  llvm_unreachable("Not yet implemented");
+}
+
+void InstARM32Pop::dump(const Cfg *Func) const {
+  if (!ALLOW_DUMP)
+    return;
+  Ostream &Str = Func->getContext()->getStrDump();
+  Str << "pop"
+      << " ";
+  for (SizeT I = 0; I < Dests.size(); ++I) {
+    if (I > 0)
+      Str << ", ";
+    Dests[I]->dump(Func);
+  }
+}
+
+void InstARM32Push::emit(const Cfg *Func) const {
+  if (!ALLOW_DUMP)
+    return;
+  assert(getSrcSize() > 0);
+  Ostream &Str = Func->getContext()->getStrEmit();
+  Str << "\t"
+      << "push"
+      << "\t{";
+  emitSources(Func);
+  Str << "}";
+}
+
+void InstARM32Push::emitIAS(const Cfg *Func) const {
+  (void)Func;
+  llvm_unreachable("Not yet implemented");
+}
+
+void InstARM32Push::dump(const Cfg *Func) const {
+  if (!ALLOW_DUMP)
+    return;
+  Ostream &Str = Func->getContext()->getStrDump();
+  Str << "push"
+      << " ";
+  dumpSources(Func);
+}
+
 void InstARM32Ret::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   assert(getSrcSize() > 0);
   Variable *LR = llvm::cast<Variable>(getSrc(0));
   assert(LR->hasReg());
   assert(LR->getRegNum() == RegARM32::Reg_lr);
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\t"
       << "bx"
@@ skipping 109 matching lines @@
       getIndex()->dump(Func);
     else
       getIndex()->dump(Str);
     if (getShiftOp() != kNoShift) {
       Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " #"
           << getShiftAmt();
     }
   } else {
     getOffset()->dump(Func, Str);
   }
-  Str << "] AddrMode==" << getAddrMode() << "\n";
+  Str << "] AddrMode==" << getAddrMode();
 }
 
 void OperandARM32FlexImm::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   uint32_t Imm = getImm();
   uint32_t RotateAmt = getRotateAmt();
   Str << "#" << Utils::rotateRight32(Imm, 2 * RotateAmt);
 }
@@ skipping 28 matching lines @@
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     if (Func)
       getShiftAmt()->dump(Func);
     else
       getShiftAmt()->dump(Str);
   }
 }
 
 } // end of namespace Ice