OLD | NEW |
1 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=d
ynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM | 1 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=d
ynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM |
2 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=d
ynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM | 2 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=d
ynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM |
3 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=d
ynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB | 3 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=d
ynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB |
4 ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple
=thumbv8-apple-ios | FileCheck %s --check-prefix=THUMB | 4 ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple
=thumbv8-apple-ios | FileCheck %s --check-prefix=THUMB |
5 | 5 |
6 define i32 @t1(i1 %c) nounwind readnone { | 6 define i32 @t1(i1 %c) nounwind readnone { |
7 entry: | 7 entry: |
8 ; ARM: t1 | 8 ; ARM: t1 |
9 ; ARM: movw r{{[1-9]}}, #10 | 9 ; ARM: movw r{{[1-9]}}, #10 |
10 ; ARM: cmp r0, #0 | 10 ; ARM: tst r0, #1 |
11 ; ARM: moveq r{{[1-9]}}, #20 | 11 ; ARM: moveq r{{[1-9]}}, #20 |
12 ; ARM: mov r0, r{{[1-9]}} | 12 ; ARM: mov r0, r{{[1-9]}} |
13 ; THUMB: t1 | 13 ; THUMB: t1 |
14 ; THUMB: movs r{{[1-9]}}, #10 | 14 ; THUMB: movs r{{[1-9]}}, #10 |
15 ; THUMB: cmp r0, #0 | 15 ; THUMB: tst.w r0, #1 |
16 ; THUMB: it eq | 16 ; THUMB: it eq |
17 ; THUMB: moveq r{{[1-9]}}, #20 | 17 ; THUMB: moveq r{{[1-9]}}, #20 |
18 ; THUMB: mov r0, r{{[1-9]}} | 18 ; THUMB: mov r0, r{{[1-9]}} |
19 %0 = select i1 %c, i32 10, i32 20 | 19 %0 = select i1 %c, i32 10, i32 20 |
20 ret i32 %0 | 20 ret i32 %0 |
21 } | 21 } |
22 | 22 |
23 define i32 @t2(i1 %c, i32 %a) nounwind readnone { | 23 define i32 @t2(i1 %c, i32 %a) nounwind readnone { |
24 entry: | 24 entry: |
25 ; ARM: t2 | 25 ; ARM: t2 |
26 ; ARM: cmp r0, #0 | 26 ; ARM: tst r0, #1 |
27 ; ARM: moveq r{{[1-9]}}, #20 | 27 ; ARM: moveq r{{[1-9]}}, #20 |
28 ; ARM: mov r0, r{{[1-9]}} | 28 ; ARM: mov r0, r{{[1-9]}} |
29 ; THUMB: t2 | 29 ; THUMB: t2 |
30 ; THUMB: cmp r0, #0 | 30 ; THUMB: tst.w r0, #1 |
31 ; THUMB: it eq | 31 ; THUMB: it eq |
32 ; THUMB: moveq r{{[1-9]}}, #20 | 32 ; THUMB: moveq r{{[1-9]}}, #20 |
33 ; THUMB: mov r0, r{{[1-9]}} | 33 ; THUMB: mov r0, r{{[1-9]}} |
34 %0 = select i1 %c, i32 %a, i32 20 | 34 %0 = select i1 %c, i32 %a, i32 20 |
35 ret i32 %0 | 35 ret i32 %0 |
36 } | 36 } |
37 | 37 |
38 define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone { | 38 define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone { |
39 entry: | 39 entry: |
40 ; ARM: t3 | 40 ; ARM: t3 |
41 ; ARM: cmp r0, #0 | 41 ; ARM: tst r0, #1 |
42 ; ARM: movne r2, r1 | 42 ; ARM: movne r2, r1 |
43 ; ARM: add r0, r2, r1 | 43 ; ARM: add r0, r2, r1 |
44 ; THUMB: t3 | 44 ; THUMB: t3 |
45 ; THUMB: cmp r0, #0 | 45 ; THUMB: tst.w r0, #1 |
46 ; THUMB: it ne | 46 ; THUMB: it ne |
47 ; THUMB: movne r2, r1 | 47 ; THUMB: movne r2, r1 |
48 ; THUMB: add.w r0, r2, r1 | 48 ; THUMB: add.w r0, r2, r1 |
49 %0 = select i1 %c, i32 %a, i32 %b | 49 %0 = select i1 %c, i32 %a, i32 %b |
50 %1 = add i32 %0, %a | 50 %1 = add i32 %0, %a |
51 ret i32 %1 | 51 ret i32 %1 |
52 } | 52 } |
53 | 53 |
54 define i32 @t4(i1 %c) nounwind readnone { | 54 define i32 @t4(i1 %c) nounwind readnone { |
55 entry: | 55 entry: |
56 ; ARM: t4 | 56 ; ARM: t4 |
57 ; ARM: mvn r{{[1-9]}}, #9 | 57 ; ARM: mvn r{{[1-9]}}, #9 |
58 ; ARM: cmp r0, #0 | 58 ; ARM: tst r0, #1 |
59 ; ARM: mvneq r{{[1-9]}}, #0 | 59 ; ARM: mvneq r{{[1-9]}}, #0 |
60 ; ARM: mov r0, r{{[1-9]}} | 60 ; ARM: mov r0, r{{[1-9]}} |
61 ; THUMB-LABEL: t4 | 61 ; THUMB-LABEL: t4 |
62 ; THUMB: mvn [[REG:r[1-9]+]], #9 | 62 ; THUMB: mvn [[REG:r[1-9]+]], #9 |
63 ; THUMB: cmp r0, #0 | 63 ; THUMB: tst.w r0, #1 |
64 ; THUMB: it eq | 64 ; THUMB: it eq |
65 ; THUMB: mvneq [[REG]], #0 | 65 ; THUMB: mvneq [[REG]], #0 |
66 ; THUMB: mov r0, [[REG]] | 66 ; THUMB: mov r0, [[REG]] |
67 %0 = select i1 %c, i32 -10, i32 -1 | 67 %0 = select i1 %c, i32 -10, i32 -1 |
68 ret i32 %0 | 68 ret i32 %0 |
69 } | 69 } |
70 | 70 |
71 define i32 @t5(i1 %c, i32 %a) nounwind readnone { | 71 define i32 @t5(i1 %c, i32 %a) nounwind readnone { |
72 entry: | 72 entry: |
73 ; ARM: t5 | 73 ; ARM: t5 |
74 ; ARM: cmp r0, #0 | 74 ; ARM: tst r0, #1 |
75 ; ARM: mvneq r{{[1-9]}}, #1 | 75 ; ARM: mvneq r{{[1-9]}}, #1 |
76 ; ARM: mov r0, r{{[1-9]}} | 76 ; ARM: mov r0, r{{[1-9]}} |
77 ; THUMB: t5 | 77 ; THUMB: t5 |
78 ; THUMB: cmp r0, #0 | 78 ; THUMB: tst.w r0, #1 |
79 ; THUMB: it eq | 79 ; THUMB: it eq |
80 ; THUMB: mvneq r{{[1-9]}}, #1 | 80 ; THUMB: mvneq r{{[1-9]}}, #1 |
81 ; THUMB: mov r0, r{{[1-9]}} | 81 ; THUMB: mov r0, r{{[1-9]}} |
82 %0 = select i1 %c, i32 %a, i32 -2 | 82 %0 = select i1 %c, i32 %a, i32 -2 |
83 ret i32 %0 | 83 ret i32 %0 |
84 } | 84 } |
85 | 85 |
86 ; Check one large negative immediates. | 86 ; Check one large negative immediates. |
87 define i32 @t6(i1 %c, i32 %a) nounwind readnone { | 87 define i32 @t6(i1 %c, i32 %a) nounwind readnone { |
88 entry: | 88 entry: |
89 ; ARM: t6 | 89 ; ARM: t6 |
90 ; ARM: cmp r0, #0 | 90 ; ARM: tst r0, #1 |
91 ; ARM: mvneq r{{[1-9]}}, #978944 | 91 ; ARM: mvneq r{{[1-9]}}, #978944 |
92 ; ARM: mov r0, r{{[1-9]}} | 92 ; ARM: mov r0, r{{[1-9]}} |
93 ; THUMB: t6 | 93 ; THUMB: t6 |
94 ; THUMB: cmp r0, #0 | 94 ; THUMB: tst.w r0, #1 |
95 ; THUMB: it eq | 95 ; THUMB: it eq |
96 ; THUMB: mvneq r{{[1-9]}}, #978944 | 96 ; THUMB: mvneq r{{[1-9]}}, #978944 |
97 ; THUMB: mov r0, r{{[1-9]}} | 97 ; THUMB: mov r0, r{{[1-9]}} |
98 %0 = select i1 %c, i32 %a, i32 -978945 | 98 %0 = select i1 %c, i32 %a, i32 -978945 |
99 ret i32 %0 | 99 ret i32 %0 |
100 } | 100 } |
OLD | NEW |