Subzero ARM: lower alloca instruction.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
@@ skipping 120 matching lines @@
 const uint32_t X86_STACK_ALIGNMENT_BYTES = 16;
 // Size of the return address on the stack
 const uint32_t X86_RET_IP_SIZE_BYTES = 4;
 // The base 2 logarithm of the width in bytes of the smallest stack slot
 const uint32_t X86_LOG2_OF_MIN_STACK_SLOT_SIZE = 2;
 // The base 2 logarithm of the width in bytes of the largest stack slot
 const uint32_t X86_LOG2_OF_MAX_STACK_SLOT_SIZE = 4;
 // The number of different NOP instructions
 const uint32_t X86_NUM_NOP_VARIANTS = 5;
 
-// Value and Alignment are in bytes.  Return Value adjusted to the next
-// highest multiple of Alignment.
-uint32_t applyAlignment(uint32_t Value, uint32_t Alignment) {
-  // power of 2
-  assert((Alignment & (Alignment - 1)) == 0);
-  return (Value + Alignment - 1) & -Alignment;
-}
-
 // Value is in bytes. Return Value adjusted to the next highest multiple
 // of the stack alignment.
 uint32_t applyStackAlignment(uint32_t Value) {
-  return applyAlignment(Value, X86_STACK_ALIGNMENT_BYTES);
+  return Utils::applyAlignment(Value, X86_STACK_ALIGNMENT_BYTES);
 }
 
 // In some cases, there are x-macros tables for both high-level and
 // low-level instructions/operands that use the same enum key value.
 // The tables are kept separate to maintain a proper separation
 // between abstraction layers.  There is a risk that the tables could
 // get out of sync if enum values are reordered or if entries are
 // added or deleted.  The following dummy namespaces use
 // static_asserts to ensure everything is kept in sync.
 
@@ skipping 787 matching lines @@
   }
 
   // Align the variables area. SpillAreaPaddingBytes is the size of
   // the region after the preserved registers and before the spill
   // areas.
   uint32_t SpillAreaPaddingBytes = 0;
   if (SpillAreaAlignmentBytes) {
     assert(SpillAreaAlignmentBytes <= X86_STACK_ALIGNMENT_BYTES);
     uint32_t PaddingStart = X86_RET_IP_SIZE_BYTES + PreservedRegsSizeBytes;
     uint32_t SpillAreaStart =
-        applyAlignment(PaddingStart, SpillAreaAlignmentBytes);
+        Utils::applyAlignment(PaddingStart, SpillAreaAlignmentBytes);
     SpillAreaPaddingBytes = SpillAreaStart - PaddingStart;
     SpillAreaSizeBytes += SpillAreaPaddingBytes;
   }
 
   // If there are separate globals and locals areas, make sure the
   // locals area is aligned by padding the end of the globals area.
   uint32_t GlobalsAndSubsequentPaddingSize = GlobalsSize;
   if (LocalsSlotsAlignmentBytes) {
     assert(LocalsSlotsAlignmentBytes <= SpillAreaAlignmentBytes);
     GlobalsAndSubsequentPaddingSize =
-        applyAlignment(GlobalsSize, LocalsSlotsAlignmentBytes);
+        Utils::applyAlignment(GlobalsSize, LocalsSlotsAlignmentBytes);
     SpillAreaSizeBytes += GlobalsAndSubsequentPaddingSize - GlobalsSize;
   }
 
   // Align esp if necessary.
   if (NeedsStackAlignment) {
     uint32_t StackOffset = X86_RET_IP_SIZE_BYTES + PreservedRegsSizeBytes;
     uint32_t StackSize = applyStackAlignment(StackOffset + SpillAreaSizeBytes);
     SpillAreaSizeBytes = StackSize - StackOffset;
   }
 
@@ skipping 272 matching lines @@
 
 void TargetX8632::lowerAlloca(const InstAlloca *Inst) {
   IsEbpBasedFrame = true;
   // Conservatively require the stack to be aligned.  Some stack
   // adjustment operations implemented below assume that the stack is
   // aligned before the alloca.  All the alloca code ensures that the
   // stack alignment is preserved after the alloca.  The stack alignment
   // restriction can be relaxed in some cases.
   NeedsStackAlignment = true;
 
-  // TODO(sehr,stichnot): minimize the number of adjustments of esp, etc.
+  // TODO(stichnot): minimize the number of adjustments of esp, etc.
   Variable *esp = getPhysicalRegister(RegX8632::Reg_esp);
   Operand *TotalSize = legalize(Inst->getSizeInBytes());
   Variable *Dest = Inst->getDest();
   uint32_t AlignmentParam = Inst->getAlignInBytes();
   // For default align=0, set it to the real value 1, to avoid any
   // bit-manipulation problems below.
   AlignmentParam = std::max(AlignmentParam, 1u);
 
   // LLVM enforces power of 2 alignment.
-  assert((AlignmentParam & (AlignmentParam - 1)) == 0);
-  assert((X86_STACK_ALIGNMENT_BYTES & (X86_STACK_ALIGNMENT_BYTES - 1)) == 0);
+  assert(llvm::isPowerOf2_32(AlignmentParam));
+  assert(llvm::isPowerOf2_32(X86_STACK_ALIGNMENT_BYTES));
 
   uint32_t Alignment = std::max(AlignmentParam, X86_STACK_ALIGNMENT_BYTES);
   if (Alignment > X86_STACK_ALIGNMENT_BYTES) {
     _and(esp, Ctx->getConstantInt32(-Alignment));
   }
-  if (ConstantInteger32 *ConstantTotalSize =
+  if (const auto *ConstantTotalSize =
           llvm::dyn_cast<ConstantInteger32>(TotalSize)) {
     uint32_t Value = ConstantTotalSize->getValue();
-    Value = applyAlignment(Value, Alignment);
+    Value = Utils::applyAlignment(Value, Alignment);
     _sub(esp, Ctx->getConstantInt32(Value));
   } else {
     // Non-constant sizes need to be adjusted to the next highest
     // multiple of the required alignment at runtime.
     Variable *T = makeReg(IceType_i32);
     _mov(T, TotalSize);
     _add(T, Ctx->getConstantInt32(Alignment - 1));
     _and(T, Ctx->getConstantInt32(-Alignment));
     _sub(esp, T);
   }
@@ skipping 3746 matching lines @@
   case FT_Asm:
   case FT_Iasm: {
     OstreamLocker L(Ctx);
     emitConstantPool<PoolTypeConverter<float>>(Ctx);
     emitConstantPool<PoolTypeConverter<double>>(Ctx);
   } break;
   }
 }
 
 } // end of namespace Ice