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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef V8_X64_ASSEMBLER_X64_INL_H_ | 5 #ifndef V8_X64_ASSEMBLER_X64_INL_H_ |
| 6 #define V8_X64_ASSEMBLER_X64_INL_H_ | 6 #define V8_X64_ASSEMBLER_X64_INL_H_ |
| 7 | 7 |
| 8 #include "src/x64/assembler-x64.h" | 8 #include "src/x64/assembler-x64.h" |
| 9 | 9 |
| 10 #include "src/base/cpu.h" | 10 #include "src/base/cpu.h" |
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| 260 | 260 |
| 261 void Assembler::emit_vex_prefix(Register reg, Register vreg, const Operand& rm, | 261 void Assembler::emit_vex_prefix(Register reg, Register vreg, const Operand& rm, |
| 262 VectorLength l, SIMDPrefix pp, LeadingOpcode mm, | 262 VectorLength l, SIMDPrefix pp, LeadingOpcode mm, |
| 263 VexW w) { | 263 VexW w) { |
| 264 XMMRegister ireg = {reg.code()}; | 264 XMMRegister ireg = {reg.code()}; |
| 265 XMMRegister ivreg = {vreg.code()}; | 265 XMMRegister ivreg = {vreg.code()}; |
| 266 emit_vex_prefix(ireg, ivreg, rm, l, pp, mm, w); | 266 emit_vex_prefix(ireg, ivreg, rm, l, pp, mm, w); |
| 267 } | 267 } |
| 268 | 268 |
| 269 | 269 |
| 270 Address Assembler::target_address_at(Address pc, Address constant_pool) { | 270 Address Assembler::target_address_at(Address pc, |
| 271 ConstantPoolArray* constant_pool) { |
| 271 return Memory::int32_at(pc) + pc + 4; | 272 return Memory::int32_at(pc) + pc + 4; |
| 272 } | 273 } |
| 273 | 274 |
| 274 | 275 |
| 275 void Assembler::set_target_address_at(Address pc, Address constant_pool, | 276 void Assembler::set_target_address_at(Address pc, |
| 277 ConstantPoolArray* constant_pool, |
| 276 Address target, | 278 Address target, |
| 277 ICacheFlushMode icache_flush_mode) { | 279 ICacheFlushMode icache_flush_mode) { |
| 278 Memory::int32_at(pc) = static_cast<int32_t>(target - pc - 4); | 280 Memory::int32_at(pc) = static_cast<int32_t>(target - pc - 4); |
| 279 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { | 281 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { |
| 280 CpuFeatures::FlushICache(pc, sizeof(int32_t)); | 282 CpuFeatures::FlushICache(pc, sizeof(int32_t)); |
| 281 } | 283 } |
| 282 } | 284 } |
| 283 | 285 |
| 284 | 286 |
| 285 void Assembler::deserialization_set_target_internal_reference_at( | 287 void Assembler::deserialization_set_target_internal_reference_at( |
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| 661 | 663 |
| 662 void Operand::set_disp64(int64_t disp) { | 664 void Operand::set_disp64(int64_t disp) { |
| 663 DCHECK_EQ(1, len_); | 665 DCHECK_EQ(1, len_); |
| 664 int64_t* p = reinterpret_cast<int64_t*>(&buf_[len_]); | 666 int64_t* p = reinterpret_cast<int64_t*>(&buf_[len_]); |
| 665 *p = disp; | 667 *p = disp; |
| 666 len_ += sizeof(disp); | 668 len_ += sizeof(disp); |
| 667 } | 669 } |
| 668 } } // namespace v8::internal | 670 } } // namespace v8::internal |
| 669 | 671 |
| 670 #endif // V8_X64_ASSEMBLER_X64_INL_H_ | 672 #endif // V8_X64_ASSEMBLER_X64_INL_H_ |
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