Fix issues with Arm's use of embedded constant pools

src/mips/assembler-mips.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 308 matching lines @@
 
 
 void Assembler::Align(int m) {
   DCHECK(m >= 4 && base::bits::IsPowerOfTwo32(m));
   while ((pc_offset() & (m - 1)) != 0) {
     nop();
   }
 }
 
 
+void Assembler::DataAlign(int m) {
+  DCHECK(m >= 2 && base::bits::IsPowerOfTwo32(m));
+  while ((pc_offset() & (m - 1)) != 0) {
+    db(0);
+  }
+}
+
+
 void Assembler::CodeTargetAlign() {
   // No advantage to aligning branch/call targets to more than
   // single instruction, that I am aware of.
   Align(4);
 }
 
 
 Register Assembler::GetRtReg(Instr instr) {
   Register rt;
   rt.code_ = (instr & kRtFieldMask) >> kRtShift;
@@ skipping 2690 matching lines @@
   if (patched) {
     CpuFeatures::FlushICache(pc + 2, sizeof(Address));
   }
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS