Use R0/R1 instead of R4/R5 for ARM eh_return return values

lib/Target/ARM/ARMFrameLowering.cpp

 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the ARM implementation of TargetFrameLowering class.
@@ skipping 948 matching lines @@
       // @llvm.returnaddress is called. If LR is returned for
       // @llvm.returnaddress then it's already added to the function and
       // entry block live-in sets.
       bool isKill = true;
       if (Reg == ARM::LR) {
         if (MF.getFrameInfo()->isReturnAddressTaken() &&
             MF.getRegInfo().isLiveIn(Reg))
           isKill = false;
       }
 
+      // @LOCALMOD-START
+      // Functions which call EHReturn spill all CSRs plus R0/R1
+      if ((Reg == ARM::R0 || Reg == ARM::R1) &&
+          MF.getRegInfo().isLiveIn(Reg)) {
+        assert(MF.getMMI().callsEHReturn());
+        isKill = false;
+      }
+      // @LOCALMOD-END
+
       if (isKill)
         MBB.addLiveIn(Reg);
 
       // If NoGap is true, push consecutive registers and then leave the rest
       // for other instructions. e.g.
       // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
       if (NoGap && LastReg && LastReg != Reg-1)
         break;
       LastReg = Reg;
       Regs.push_back(std::make_pair(Reg, isKill));
@@ skipping 39 matching lines @@
   bool isTailCall = (RetOpcode == ARM::TCRETURNdi ||
                      RetOpcode == ARM::TCRETURNri);
   bool isInterrupt =
       RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
 
   SmallVector<unsigned, 4> Regs;
   unsigned i = CSI.size();
   while (i != 0) {
     unsigned LastReg = 0;
     bool DeleteRet = false;
+    unsigned SkippedPop = 0; // @LOCALMOD
     for (; i != 0; --i) {
       unsigned Reg = CSI[i-1].getReg();
       if (!(Func)(Reg, STI.isTargetDarwin())) continue;
 
       // The aligned reloads from area DPRCS2 are not inserted here.
       if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
         continue;
 
+      // @LOCALMOD-START
+      // Functions which call EHReturn spill all of their CSRs plus R0 and R1,
+      // (the EHReturn return value registers). Epilogs which return via
+      // EHreturn pop all of them, but epilogs which return via normal return
+      // must not restore R0 and R1, as that would clobber the return value.
+      if (MF.getMMI().callsEHReturn() &&
+          RetOpcode != ARM::ARMeh_return &&
+          (Reg == ARM::R0 || Reg == ARM::R1)) {
+        SkippedPop++;
+        continue;
+      }
+      // @LOCALMOD-END
+
       if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
           STI.hasV5TOps() &&
           !STI.isTargetNaCl() /* @LOCALMOD */) {
         Reg = ARM::PC;
         LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
         // Fold the return instruction into the LDM.
         DeleteRet = true;
       }
 
       // If NoGap is true, pop consecutive registers and then leave the rest
       // for other instructions. e.g.
       // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
       if (NoGap && LastReg && LastReg != Reg-1)
         break;
 
       LastReg = Reg;
       Regs.push_back(Reg);
     }
 
+    // @LOCALMOD-START
+    if (SkippedPop) {
+      // We need to increment the stack pointer to compensate for the skipped
+      // pops. However we cannot directly increment it because the epilog
+      // insertion code places the stack pointer restore before the CSR restores;

[jvoung (off chromium), 2015/06/03 17:19:38]

80 col

[Derek Schuff, 2015/06/03 20:50:57]

Done.

+      // it does this by finding the first instruction that's not a pop.
+      // If we put an add here, the restore would go in between the restore of
+      // the FP registers and the GPRs, instead of before the FP restore. So
+      // use a pop into R12 to adjust SP.
+      while(SkippedPop--)
+         AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
+                         .addReg(ARM::SP)).addReg(ARM::R12);
+    }
+    // @LOCALMOD-END
+
     if (Regs.empty())
       continue;
     if (Regs.size() > 1 || LdrOpc == 0) {
       MachineInstrBuilder MIB =
-        AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
-                       .addReg(ARM::SP));
+          AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
+                                      .addReg(ARM::SP));

[jvoung (off chromium), 2015/06/03 17:19:38]

revert whitespace change?

[Derek Schuff, 2015/06/03 20:50:57]

Done.

       for (unsigned i = 0, e = Regs.size(); i < e; ++i)
         MIB.addReg(Regs[i], getDefRegState(true));
       if (DeleteRet) {
         MIB.copyImplicitOps(&*MI);
         MI->eraseFromParent();
       }
       MI = MIB;
     } else if (Regs.size() == 1) {
       // If we adjusted the reg to PC from LR above, switch it back here. We
       // only do that for LDM.
@@ skipping 1094 matching lines @@
   GetMBB->addSuccessor(AllocMBB);
 
   McrMBB->addSuccessor(GetMBB);
 
   PrevStackMBB->addSuccessor(McrMBB);
 
 #ifdef XDEBUG
   MF.verify();
 #endif
 }