Subzero ARM: lowerLoad and lowerStore.

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 \
@@ skipping 1285 matching lines @@
 }
 ; CHECK-LABEL: load64
 ; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
 ; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]]
 ; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]+0x4]
 ;
 ; OPTM1-LABEL: load64
 ; OPTM1: mov e{{..}},DWORD PTR [e{{..}}]
 ; OPTM1: mov e{{..}},DWORD PTR [e{{..}}+0x4]
 
+; ARM32-LABEL: load64
+; ARM32: ldr r{{.*}}, [r[[REG:.*]]]
+; ARM32: ldr r{{.*}}, [r[[REG]], #4]
+
 define internal void @store64(i32 %a, i64 %value) {
 entry:
   %__2 = inttoptr i32 %a to i64*
   store i64 %value, i64* %__2, align 1
   ret void
 }
 ; CHECK-LABEL: store64
 ; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
 ; CHECK: mov DWORD PTR [e[[REGISTER]]+0x4],
 ; CHECK: mov DWORD PTR [e[[REGISTER]]],
 ;
 ; OPTM1-LABEL: store64
 ; OPTM1: mov DWORD PTR [e[[REGISTER:[a-z]+]]+0x4],
 ; OPTM1: mov DWORD PTR [e[[REGISTER]]],
 
+; ARM32-LABEL: store64
+; ARM32: str r{{.*}}, [r[[REG:.*]], #4]
+; ARM32: str r{{.*}}, [r[[REG]]]
+
 define internal void @store64Const(i32 %a) {
 entry:
   %__1 = inttoptr i32 %a to i64*
   store i64 -2401053092306725256, i64* %__1, align 1
   ret void
 }
 ; CHECK-LABEL: store64Const
 ; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
 ; CHECK: mov DWORD PTR [e[[REGISTER]]+0x4],0xdeadbeef
 ; CHECK: mov DWORD PTR [e[[REGISTER]]],0x12345678
 ;
 ; OPTM1-LABEL: store64Const
 ; OPTM1: mov DWORD PTR [e[[REGISTER:[a-z]+]]+0x4],0xdeadbeef
 ; OPTM1: mov DWORD PTR [e[[REGISTER]]],0x12345678
 
+; ARM32-LABEL: store64Const
+; ARM32: movw [[REG1:.*]], #48879 ; 0xbeef
+; ARM32: movt [[REG1:.*]], #57005 ; 0xdead
+; ARM32: movw [[REG2:.*]], #22136 ; 0x5678
+; ARM32: movt [[REG2:.*]], #4660  ; 0x1234
+; ARM32: str [[REG1]], [r[[REG:.*]], #4]
+; ARM32: str [[REG2]], [r[[REG]]]
+
 define internal i64 @select64VarVar(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ult i64 %a, %b
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 }
 ; CHECK-LABEL: select64VarVar
 ; CHECK: cmp
 ; CHECK: jb
 ; CHECK: ja
@@ skipping 109 matching lines @@
   ret void
 }
 ; The following checks are not strictly necessary since one of the RUN
 ; lines actually runs the output through the assembler.
 ; CHECK-LABEL: icmpLt64Imm
 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
 ; OPTM1-LABEL: icmpLt64Imm
 ; OPTM1-NOT: cmp 0x{{[0-9a-f]+}},
 ; ARM32-LABEL: icmpLt64Imm
 ; ARM32-NOT: cmp #{{[0-9a-f]+}},