Subzero ARM: do lowerIcmp, lowerBr, and a bit of lowerCall.

src/IceConditionCodesARM32.h

Index: src/IceConditionCodesARM32.h
diff --git a/src/IceConditionCodesARM32.h b/src/IceConditionCodesARM32.h
new file mode 100644
index 0000000000000000000000000000000000000000..b98c7706c92a71a3f6aa65513a9a63b2e1934fb6
--- /dev/null
+++ b/src/IceConditionCodesARM32.h
@@ -0,0 +1,39 @@
+//===- subzero/src/IceConditionCodesARM32.h - Condition Codes ---*- C++ -*-===//
+//
+//                        The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the condition codes for ARM32.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ICECONDITIONCODESARM32_H
+#define SUBZERO_SRC_ICECONDITIONCODESARM32_H
+
+#include "IceDefs.h"
+#include "IceInstARM32.def"
+
+namespace Ice {
+
+class CondARM32 {
+  CondARM32() = delete;
+  CondARM32(const CondARM32 &) = delete;
+  CondARM32 &operator=(const CondARM32 &) = delete;
+
+public:
+  // An enum of codes used for conditional instructions. The enum value
+  // should match the value used to encode operands in binary instructions.
+  enum Cond {
+#define X(tag, encode, opp, emit) tag = encode,
+    ICEINSTARM32COND_TABLE
+#undef X
+  };
+};
+
+} // end of namespace Ice
+
+#endif // SUBZERO_SRC_ICECONDITIONCODESARM32_H