Subzero ARM: do lowerIcmp, lowerBr, and a bit of lowerCall.

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
-; RUN:   | FileCheck %s
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 \
-; RUN:   | FileCheck --check-prefix=OPTM1 %s
+; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
+; RUN:   --target x8632 -i %s --args -O2 \
+; RUN:   | %if --need=target_X8632 --command FileCheck %s
+
+; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
+; RUN:   --target x8632 -i %s --args -Om1 \
+; RUN:   | %if --need=target_X8632 --command FileCheck --check-prefix=OPTM1 %s
+
+; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented)
+; once enough infrastructure is in. Also, switch to --filetype=obj
+; when possible.
+; RUN: %if --need=target_ARM32 --command %p2i --filetype=asm --assemble \
+; RUN:   --disassemble --target arm32 -i %s --args -O2 --skip-unimplemented \
+; RUN:   | %if --need=target_ARM32 --command FileCheck --check-prefix ARM32 %s
 
 @__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
 @__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
 @__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
 @__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4
 
 define internal i32 @ignore64BitArg(i64 %a, i32 %b, i64 %c) {
 entry:
   ret i32 %b
 }
@@ skipping 88 matching lines @@
   ret i64 %a
 }
 ; CHECK-LABEL: return64BitArg
 ; CHECK: mov     {{.*}},DWORD PTR [esp+0x4]
 ; CHECK: mov     {{.*}},DWORD PTR [esp+0x8]
 ;
 ; OPTM1-LABEL: return64BitArg
 ; OPTM1: mov     {{.*}},DWORD PTR [esp+0x4]
 ; OPTM1: mov     {{.*}},DWORD PTR [esp+0x8]
 
+; Nothing to do for ARM O2 -- arg and return value are in r0,r1.
+; ARM32-LABEL: return64BitArg
+; ARM32-NEXT: bx lr
+
 define internal i64 @return64BitConst() {
 entry:
   ret i64 -2401053092306725256
 }
 ; CHECK-LABEL: return64BitConst
 ; CHECK: mov     eax,0x12345678
 ; CHECK: mov     edx,0xdeadbeef
 ;
 ; OPTM1-LABEL: return64BitConst
 ; OPTM1: mov     eax,0x12345678
 ; OPTM1: mov     edx,0xdeadbeef
 
+; ARM32-LABEL: return64BitConst
+; ARM32: movw r0, #22136 ; 0x5678
+; ARM32: movt r0, #4660  ; 0x1234
+; ARM32: movw r1, #48879 ; 0xbeef
+; ARM32: movt r1, #57005 ; 0xdead
+
 define internal i64 @add64BitSigned(i64 %a, i64 %b) {
 entry:
   %add = add i64 %b, %a
   ret i64 %add
 }
 ; CHECK-LABEL: add64BitSigned
 ; CHECK: add
 ; CHECK: adc
 ;
 ; OPTM1-LABEL: add64BitSigned
 ; OPTM1: add
 ; OPTM1: adc
 
+; ARM32-LABEL: add64BitSigned
+; ARM32: adds
+; ARM32: adc
+
 define internal i64 @add64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %add = add i64 %b, %a
   ret i64 %add
 }
 ; CHECK-LABEL: add64BitUnsigned
 ; CHECK: add
 ; CHECK: adc
 ;
 ; OPTM1-LABEL: add64BitUnsigned
 ; OPTM1: add
 ; OPTM1: adc
 
+; ARM32-LABEL: add64BitUnsigned
+; ARM32: adds
+; ARM32: adc
+
 define internal i64 @sub64BitSigned(i64 %a, i64 %b) {
 entry:
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
 ; CHECK-LABEL: sub64BitSigned
 ; CHECK: sub
 ; CHECK: sbb
 ;
 ; OPTM1-LABEL: sub64BitSigned
 ; OPTM1: sub
 ; OPTM1: sbb
 
+; ARM32-LABEL: sub64BitSigned
+; ARM32: subs
+; ARM32: sbc
+
 define internal i64 @sub64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
 ; CHECK-LABEL: sub64BitUnsigned
 ; CHECK: sub
 ; CHECK: sbb
 ;
 ; OPTM1-LABEL: sub64BitUnsigned
 ; OPTM1: sub
 ; OPTM1: sbb
 
+; ARM32-LABEL: sub64BitUnsigned
+; ARM32: subs
+; ARM32: sbc
+
 define internal i64 @mul64BitSigned(i64 %a, i64 %b) {
 entry:
   %mul = mul i64 %b, %a
   ret i64 %mul
 }
 ; CHECK-LABEL: mul64BitSigned
 ; CHECK: imul
 ; CHECK: imul
 ; CHECK: mul
 ; CHECK: add
 ; CHECK: add
 ;
 ; OPTM1-LABEL: mul64BitSigned
 ; OPTM1: imul
 ; OPTM1: imul
 ; OPTM1: mul
 ; OPTM1: add
 ; OPTM1: add
 
+; ARM32-LABEL: mul64BitSigned
+; ARM32: mul
+; ARM32: mla
+; ARM32: umull
+; ARM32: add
+
 define internal i64 @mul64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %mul = mul i64 %b, %a
   ret i64 %mul
 }
 ; CHECK-LABEL: mul64BitUnsigned
 ; CHECK: imul
 ; CHECK: imul
 ; CHECK: mul
 ; CHECK: add
 ; CHECK: add
 ;
 ; OPTM1-LABEL: mul64BitUnsigned
 ; OPTM1: imul
 ; OPTM1: imul
 ; OPTM1: mul
 ; OPTM1: add
 ; OPTM1: add
 
+; ARM32-LABEL: mul64BitUnsigned
+; ARM32: mul
+; ARM32: mla
+; ARM32: umull
+; ARM32: add
+
 define internal i64 @div64BitSigned(i64 %a, i64 %b) {
 entry:
   %div = sdiv i64 %a, %b
   ret i64 %div
 }
 ; CHECK-LABEL: div64BitSigned
 ; CHECK: call {{.*}} R_{{.*}}    __divdi3
 
 ; OPTM1-LABEL: div64BitSigned
 ; OPTM1: call {{.*}} R_{{.*}}    __divdi3
@@ skipping 177 matching lines @@
   ret i64 %and
 }
 ; CHECK-LABEL: and64BitSigned
 ; CHECK: and
 ; CHECK: and
 ;
 ; OPTM1-LABEL: and64BitSigned
 ; OPTM1: and
 ; OPTM1: and
 
+; ARM32-LABEL: and64BitSigned
+; ARM32: and
+; ARM32: and
+
 define internal i64 @and64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %and = and i64 %b, %a
   ret i64 %and
 }
 ; CHECK-LABEL: and64BitUnsigned
 ; CHECK: and
 ; CHECK: and
 ;
 ; OPTM1-LABEL: and64BitUnsigned
 ; OPTM1: and
 ; OPTM1: and
 
+; ARM32-LABEL: and64BitUnsigned
+; ARM32: and
+; ARM32: and
+
 define internal i64 @or64BitSigned(i64 %a, i64 %b) {
 entry:
   %or = or i64 %b, %a
   ret i64 %or
 }
 ; CHECK-LABEL: or64BitSigned
 ; CHECK: or
 ; CHECK: or
 ;
 ; OPTM1-LABEL: or64BitSigned
 ; OPTM1: or
 ; OPTM1: or
 
+; ARM32-LABEL: or64BitSigned
+; ARM32: orr
+; ARM32: orr
+
 define internal i64 @or64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %or = or i64 %b, %a
   ret i64 %or
 }
 ; CHECK-LABEL: or64BitUnsigned
 ; CHECK: or
 ; CHECK: or
 ;
 ; OPTM1-LABEL: or64BitUnsigned
 ; OPTM1: or
 ; OPTM1: or
 
+; ARM32-LABEL: or64BitUnsigned
+; ARM32: orr
+; ARM32: orr
+
 define internal i64 @xor64BitSigned(i64 %a, i64 %b) {
 entry:
   %xor = xor i64 %b, %a
   ret i64 %xor
 }
 ; CHECK-LABEL: xor64BitSigned
 ; CHECK: xor
 ; CHECK: xor
 ;
 ; OPTM1-LABEL: xor64BitSigned
 ; OPTM1: xor
 ; OPTM1: xor
 
+; ARM32-LABEL: xor64BitSigned
+; ARM32: eor
+; ARM32: eor
+
 define internal i64 @xor64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %xor = xor i64 %b, %a
   ret i64 %xor
 }
 ; CHECK-LABEL: xor64BitUnsigned
 ; CHECK: xor
 ; CHECK: xor
 ;
 ; OPTM1-LABEL: xor64BitUnsigned
 ; OPTM1: xor
 ; OPTM1: xor
 
+; ARM32-LABEL: xor64BitUnsigned
+; ARM32: eor
+; ARM32: eor
+
 define internal i32 @trunc64To32Signed(i64 %a) {
 entry:
   %conv = trunc i64 %a to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: trunc64To32Signed
 ; CHECK: mov     eax,DWORD PTR [esp+0x4]
 ;
 ; OPTM1-LABEL: trunc64To32Signed
 ; OPTM1: mov     eax,DWORD PTR [esp+
@@ skipping 248 matching lines @@
 ; CHECK: call
 ;
 ; OPTM1-LABEL: icmpEq64
 ; OPTM1: jne
 ; OPTM1: je
 ; OPTM1: call
 ; OPTM1: jne
 ; OPTM1: je
 ; OPTM1: call
 
+; ARM32-LABEL: icmpEq64
+; ARM32: cmp
+; ARM32: cmpeq
+; ARM32: moveq
+; ARM32: movne
+; ARM32: beq
+; ARM32: bl
+; ARM32: cmp
+; ARM32: cmpeq
+; ARM32: moveq
+; ARM32: movne
+; ARM32: beq
+; ARM32: bl
+
 declare void @func()
 
 define internal void @icmpNe64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ne i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
@@ skipping 18 matching lines @@
 ; CHECK: call
 ;
 ; OPTM1-LABEL: icmpNe64
 ; OPTM1: jne
 ; OPTM1: jne
 ; OPTM1: call
 ; OPTM1: jne
 ; OPTM1: jne
 ; OPTM1: call
 
+; ARM32-LABEL: icmpNe64
+; ARM32: cmp
+; ARM32: cmpeq
+; ARM32: movne
+; ARM32: moveq
+; ARM32: beq
+; ARM32: bl
+; ARM32: cmp
+; ARM32: cmpeq
+; ARM32: movne
+; ARM32: moveq
+; ARM32: beq
+; ARM32: bl
+
 define internal void @icmpGt64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ugt i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
@@ skipping 20 matching lines @@
 ; OPTM1-LABEL: icmpGt64
 ; OPTM1: ja
 ; OPTM1: jb
 ; OPTM1: ja
 ; OPTM1: call
 ; OPTM1: jg
 ; OPTM1: jl
 ; OPTM1: ja
 ; OPTM1: call
 
+; ARM32-LABEL: icmpGt64
+; ARM32: cmp
+; ARM32: cmpeq
+; ARM32: movhi
+; ARM32: movls
+; ARM32: beq
+; ARM32: bl
+; ARM32: cmp
+; ARM32: sbcs
+; ARM32: movlt
+; ARM32: movge
+; ARM32: beq
+; ARM32: bl
+
 define internal void @icmpGe64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp uge i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
@@ skipping 20 matching lines @@
 ; OPTM1-LABEL: icmpGe64
 ; OPTM1: ja
 ; OPTM1: jb
 ; OPTM1: jae
 ; OPTM1: call
 ; OPTM1: jg
 ; OPTM1: jl
 ; OPTM1: jae
 ; OPTM1: call
 
+; ARM32-LABEL: icmpGe64
+; ARM32: cmp
+; ARM32: cmpeq
+; ARM32: movcs
+; ARM32: movcc
+; ARM32: beq
+; ARM32: bl
+; ARM32: cmp
+; ARM32: sbcs
+; ARM32: movge
+; ARM32: movlt
+; ARM32: beq
+; ARM32: bl
+
 define internal void @icmpLt64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ult i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
@@ skipping 20 matching lines @@
 ; OPTM1-LABEL: icmpLt64
 ; OPTM1: jb
 ; OPTM1: ja
 ; OPTM1: jb
 ; OPTM1: call
 ; OPTM1: jl
 ; OPTM1: jg
 ; OPTM1: jb
 ; OPTM1: call
 
+; ARM32-LABEL: icmpLt64
+; ARM32: cmp
+; ARM32: cmpeq
+; ARM32: movcc
+; ARM32: movcs
+; ARM32: beq
+; ARM32: bl
+; ARM32: cmp
+; ARM32: sbcs
+; ARM32: movlt
+; ARM32: movge
+; ARM32: beq
+; ARM32: bl
+
 define internal void @icmpLe64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ule i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
@@ skipping 20 matching lines @@
 ; OPTM1-LABEL: icmpLe64
 ; OPTM1: jb
 ; OPTM1: ja
 ; OPTM1: jbe
 ; OPTM1: call
 ; OPTM1: jl
 ; OPTM1: jg
 ; OPTM1: jbe
 ; OPTM1: call
 
+; ARM32-LABEL: icmpLe64
+; ARM32: cmp
+; ARM32: cmpeq
+; ARM32: movls
+; ARM32: movhi
+; ARM32: beq
+; ARM32: bl
+; ARM32: cmp
+; ARM32: sbcs
+; ARM32: movge
+; ARM32: movlt
+; ARM32: beq
+; ARM32: bl
+
 define internal i32 @icmpEq64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp eq i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpEq64Bool
 ; CHECK: jne
 ; CHECK: je
 ;
@@ skipping 311 matching lines @@
 
 if.end3:                                          ; preds = %if.then2, %if.end
   ret void
 }
 ; The following checks are not strictly necessary since one of the RUN
 ; lines actually runs the output through the assembler.
 ; CHECK-LABEL: icmpEq64Imm
 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
 ; OPTM1-LABEL: icmpEq64Imm
 ; OPTM1-LABEL-NOT: cmp 0x{{[0-9a-f]+}},
+; ARM32-LABEL: icmpEq64Imm
+; ARM32-NOT: cmp #{{[0-9a-f]+}},
 
 define internal void @icmpLt64Imm() {
 entry:
   %cmp = icmp ult i64 123, 234
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
   %cmp1 = icmp slt i64 345, 456
   br i1 %cmp1, label %if.then2, label %if.end3
 
 if.then2:                                         ; preds = %if.end
   call void @func()
   br label %if.end3
 
 if.end3:                                          ; preds = %if.then2, %if.end
   ret void
 }
 ; The following checks are not strictly necessary since one of the RUN
 ; lines actually runs the output through the assembler.
 ; CHECK-LABEL: icmpLt64Imm
 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
 ; OPTM1-LABEL: icmpLt64Imm
 ; OPTM1-NOT: cmp 0x{{[0-9a-f]+}},
+; ARM32-LABEL: icmpLt64Imm
+; ARM32-NOT: cmp #{{[0-9a-f]+}},