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Side by Side Diff: src/IceTargetLoweringARM32.h

Issue 1151663004: Subzero ARM: do lowerIcmp, lowerBr, and a bit of lowerCall. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: fix Created 5 years, 7 months ago
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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file declares the TargetLoweringARM32 class, which implements the 10 // This file declares the TargetLoweringARM32 class, which implements the
(...skipping 112 matching lines...) Expand 10 before | Expand all | Expand 10 after
123 Variable *makeVectorOfZeros(Type Ty, int32_t RegNum = Variable::NoRegister); 123 Variable *makeVectorOfZeros(Type Ty, int32_t RegNum = Variable::NoRegister);
124 124
125 void makeRandomRegisterPermutation( 125 void makeRandomRegisterPermutation(
126 llvm::SmallVectorImpl<int32_t> &Permutation, 126 llvm::SmallVectorImpl<int32_t> &Permutation,
127 const llvm::SmallBitVector &ExcludeRegisters) const override; 127 const llvm::SmallBitVector &ExcludeRegisters) const override;
128 128
129 // The following are helpers that insert lowered ARM32 instructions 129 // The following are helpers that insert lowered ARM32 instructions
130 // with minimal syntactic overhead, so that the lowering code can 130 // with minimal syntactic overhead, so that the lowering code can
131 // look as close to assembly as practical. 131 // look as close to assembly as practical.
132 132
133 void _add(Variable *Dest, Variable *Src0, Operand *Src1) { 133 void _add(Variable *Dest, Variable *Src0, Operand *Src1,
134 Context.insert(InstARM32Add::create(Func, Dest, Src0, Src1)); 134 CondARM32::Cond Pred = CondARM32::AL) {
135 Context.insert(InstARM32Add::create(Func, Dest, Src0, Src1, Pred));
135 } 136 }
136 void _adds(Variable *Dest, Variable *Src0, Operand *Src1) { 137 void _adds(Variable *Dest, Variable *Src0, Operand *Src1,
138 CondARM32::Cond Pred = CondARM32::AL) {
137 const bool SetFlags = true; 139 const bool SetFlags = true;
138 Context.insert(InstARM32Add::create(Func, Dest, Src0, Src1, SetFlags)); 140 Context.insert(
141 InstARM32Add::create(Func, Dest, Src0, Src1, Pred, SetFlags));
139 } 142 }
140 void _adc(Variable *Dest, Variable *Src0, Operand *Src1) { 143 void _adc(Variable *Dest, Variable *Src0, Operand *Src1,
141 Context.insert(InstARM32Adc::create(Func, Dest, Src0, Src1)); 144 CondARM32::Cond Pred = CondARM32::AL) {
145 Context.insert(InstARM32Adc::create(Func, Dest, Src0, Src1, Pred));
142 } 146 }
143 void _and(Variable *Dest, Variable *Src0, Operand *Src1) { 147 void _and(Variable *Dest, Variable *Src0, Operand *Src1,
144 Context.insert(InstARM32And::create(Func, Dest, Src0, Src1)); 148 CondARM32::Cond Pred = CondARM32::AL) {
149 Context.insert(InstARM32And::create(Func, Dest, Src0, Src1, Pred));
145 } 150 }
146 void _eor(Variable *Dest, Variable *Src0, Operand *Src1) { 151 void _br(CondARM32::Cond Condition, CfgNode *TargetTrue,
147 Context.insert(InstARM32Eor::create(Func, Dest, Src0, Src1)); 152 CfgNode *TargetFalse) {
153 Context.insert(
154 InstARM32Br::create(Func, TargetTrue, TargetFalse, Condition));
148 } 155 }
149 void _ldr(Variable *Dest, OperandARM32Mem *Addr) { 156 void _br(CfgNode *Target) {
150 Context.insert(InstARM32Ldr::create(Func, Dest, Addr)); 157 Context.insert(InstARM32Br::create(Func, Target));
151 } 158 }
152 void _mla(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc) { 159 void _cmp(Variable *Src0, Operand *Src1,
153 Context.insert(InstARM32Mla::create(Func, Dest, Src0, Src1, Acc)); 160 CondARM32::Cond Pred = CondARM32::AL) {
161 Context.insert(InstARM32Cmp::create(Func, Src0, Src1, Pred));
162 }
163 void _eor(Variable *Dest, Variable *Src0, Operand *Src1,
164 CondARM32::Cond Pred = CondARM32::AL) {
165 Context.insert(InstARM32Eor::create(Func, Dest, Src0, Src1, Pred));
166 }
167 void _ldr(Variable *Dest, OperandARM32Mem *Addr,
168 CondARM32::Cond Pred = CondARM32::AL) {
169 Context.insert(InstARM32Ldr::create(Func, Dest, Addr, Pred));
170 }
171 void _lsl(Variable *Dest, Variable *Src0, Operand *Src1,
172 CondARM32::Cond Pred = CondARM32::AL) {
173 Context.insert(InstARM32Lsl::create(Func, Dest, Src0, Src1, Pred));
174 }
175 void _mla(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc,
176 CondARM32::Cond Pred = CondARM32::AL) {
177 Context.insert(InstARM32Mla::create(Func, Dest, Src0, Src1, Acc, Pred));
154 } 178 }
155 // If Dest=nullptr is passed in, then a new variable is created, 179 // If Dest=nullptr is passed in, then a new variable is created,
156 // marked as infinite register allocation weight, and returned 180 // marked as infinite register allocation weight, and returned
157 // through the in/out Dest argument. 181 // through the in/out Dest argument.
158 void _mov(Variable *&Dest, Operand *Src0, 182 void _mov(Variable *&Dest, Operand *Src0,
183 CondARM32::Cond Pred = CondARM32::AL,
159 int32_t RegNum = Variable::NoRegister) { 184 int32_t RegNum = Variable::NoRegister) {
160 if (Dest == nullptr) 185 if (Dest == nullptr)
161 Dest = makeReg(Src0->getType(), RegNum); 186 Dest = makeReg(Src0->getType(), RegNum);
162 Context.insert(InstARM32Mov::create(Func, Dest, Src0)); 187 Context.insert(InstARM32Mov::create(Func, Dest, Src0, Pred));
188 }
189 void _mov_nonkillable(Variable *Dest, Operand *Src0,
190 CondARM32::Cond Pred = CondARM32::AL) {
191 Inst *NewInst = InstARM32Mov::create(Func, Dest, Src0, Pred);
192 NewInst->setDestNonKillable();
193 Context.insert(NewInst);
163 } 194 }
164 // The Operand can only be a 16-bit immediate or a ConstantRelocatable 195 // The Operand can only be a 16-bit immediate or a ConstantRelocatable
165 // (with an upper16 relocation). 196 // (with an upper16 relocation).
166 void _movt(Variable *Dest, Operand *Src0) { 197 void _movt(Variable *Dest, Operand *Src0,
167 Context.insert(InstARM32Movt::create(Func, Dest, Src0)); 198 CondARM32::Cond Pred = CondARM32::AL) {
199 Context.insert(InstARM32Movt::create(Func, Dest, Src0, Pred));
168 } 200 }
169 void _movw(Variable *Dest, Operand *Src0) { 201 void _movw(Variable *Dest, Operand *Src0,
170 Context.insert(InstARM32Movw::create(Func, Dest, Src0)); 202 CondARM32::Cond Pred = CondARM32::AL) {
203 Context.insert(InstARM32Movw::create(Func, Dest, Src0, Pred));
171 } 204 }
172 void _mul(Variable *Dest, Variable *Src0, Variable *Src1) { 205 void _mul(Variable *Dest, Variable *Src0, Variable *Src1,
173 Context.insert(InstARM32Mul::create(Func, Dest, Src0, Src1)); 206 CondARM32::Cond Pred = CondARM32::AL) {
207 Context.insert(InstARM32Mul::create(Func, Dest, Src0, Src1, Pred));
174 } 208 }
175 void _mvn(Variable *Dest, Operand *Src0) { 209 void _mvn(Variable *Dest, Operand *Src0,
176 Context.insert(InstARM32Mvn::create(Func, Dest, Src0)); 210 CondARM32::Cond Pred = CondARM32::AL) {
211 Context.insert(InstARM32Mvn::create(Func, Dest, Src0, Pred));
177 } 212 }
178 void _orr(Variable *Dest, Variable *Src0, Operand *Src1) { 213 void _orr(Variable *Dest, Variable *Src0, Operand *Src1,
179 Context.insert(InstARM32Orr::create(Func, Dest, Src0, Src1)); 214 CondARM32::Cond Pred = CondARM32::AL) {
215 Context.insert(InstARM32Orr::create(Func, Dest, Src0, Src1, Pred));
180 } 216 }
181 void _sbc(Variable *Dest, Variable *Src0, Operand *Src1) { 217 void _sbc(Variable *Dest, Variable *Src0, Operand *Src1,
182 Context.insert(InstARM32Sbc::create(Func, Dest, Src0, Src1)); 218 CondARM32::Cond Pred = CondARM32::AL) {
219 Context.insert(InstARM32Sbc::create(Func, Dest, Src0, Src1, Pred));
183 } 220 }
184 void _sub(Variable *Dest, Variable *Src0, Operand *Src1) { 221 void _sbcs(Variable *Dest, Variable *Src0, Operand *Src1,
185 Context.insert(InstARM32Sub::create(Func, Dest, Src0, Src1)); 222 CondARM32::Cond Pred = CondARM32::AL) {
223 const bool SetFlags = true;
224 Context.insert(
225 InstARM32Sbc::create(Func, Dest, Src0, Src1, Pred, SetFlags));
186 } 226 }
187 void _subs(Variable *Dest, Variable *Src0, Operand *Src1) { 227 void _sub(Variable *Dest, Variable *Src0, Operand *Src1,
228 CondARM32::Cond Pred = CondARM32::AL) {
229 Context.insert(InstARM32Sub::create(Func, Dest, Src0, Src1, Pred));
230 }
231 void _subs(Variable *Dest, Variable *Src0, Operand *Src1,
232 CondARM32::Cond Pred = CondARM32::AL) {
188 const bool SetFlags = true; 233 const bool SetFlags = true;
189 Context.insert(InstARM32Sub::create(Func, Dest, Src0, Src1, SetFlags)); 234 Context.insert(
235 InstARM32Sub::create(Func, Dest, Src0, Src1, Pred, SetFlags));
190 } 236 }
191 void _ret(Variable *LR, Variable *Src0 = nullptr) { 237 void _ret(Variable *LR, Variable *Src0 = nullptr) {
192 Context.insert(InstARM32Ret::create(Func, LR, Src0)); 238 Context.insert(InstARM32Ret::create(Func, LR, Src0));
193 } 239 }
194 void _umull(Variable *DestLo, Variable *DestHi, Variable *Src0, 240 void _umull(Variable *DestLo, Variable *DestHi, Variable *Src0,
195 Variable *Src1) { 241 Variable *Src1, CondARM32::Cond Pred = CondARM32::AL) {
196 Context.insert(InstARM32Umull::create(Func, DestLo, DestHi, Src0, Src1)); 242 Context.insert(
243 InstARM32Umull::create(Func, DestLo, DestHi, Src0, Src1, Pred));
197 // Model the modification to the second dest as a fake def. 244 // Model the modification to the second dest as a fake def.
245 // Note that the def is not predicated.
198 Context.insert(InstFakeDef::create(Func, DestHi, DestLo)); 246 Context.insert(InstFakeDef::create(Func, DestHi, DestLo));
199 } 247 }
200 248
201 bool UsesFramePointer; 249 bool UsesFramePointer;
202 bool NeedsStackAlignment; 250 bool NeedsStackAlignment;
203 llvm::SmallBitVector TypeToRegisterSet[IceType_NUM]; 251 llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
204 llvm::SmallBitVector ScratchRegs; 252 llvm::SmallBitVector ScratchRegs;
205 llvm::SmallBitVector RegsUsed; 253 llvm::SmallBitVector RegsUsed;
206 VarList PhysicalRegisters[IceType_NUM]; 254 VarList PhysicalRegisters[IceType_NUM];
207 static IceString RegNames[]; 255 static IceString RegNames[];
(...skipping 20 matching lines...) Expand all
228 276
229 private: 277 private:
230 void lowerGlobal(const VariableDeclaration &Var) const; 278 void lowerGlobal(const VariableDeclaration &Var) const;
231 ~TargetDataARM32() override {} 279 ~TargetDataARM32() override {}
232 template <typename T> static void emitConstantPool(GlobalContext *Ctx); 280 template <typename T> static void emitConstantPool(GlobalContext *Ctx);
233 }; 281 };
234 282
235 } // end of namespace Ice 283 } // end of namespace Ice
236 284
237 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H 285 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H
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