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1 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===// | 1 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file implements the InstX8632 and OperandX8632 classes, | 10 // This file implements the InstX8632 and OperandX8632 classes, |
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576 Str << " = "; | 576 Str << " = "; |
577 } | 577 } |
578 Str << "call "; | 578 Str << "call "; |
579 getCallTarget()->dump(Func); | 579 getCallTarget()->dump(Func); |
580 } | 580 } |
581 | 581 |
582 // The ShiftHack parameter is used to emit "cl" instead of "ecx" for | 582 // The ShiftHack parameter is used to emit "cl" instead of "ecx" for |
583 // shift instructions, in order to be syntactically valid. The | 583 // shift instructions, in order to be syntactically valid. The |
584 // Opcode parameter needs to be char* and not IceString because of | 584 // Opcode parameter needs to be char* and not IceString because of |
585 // template issues. | 585 // template issues. |
586 void emitTwoAddress(const char *Opcode, const Inst *Inst, const Cfg *Func, | 586 void InstX8632::emitTwoAddress(const char *Opcode, const Inst *Inst, |
587 bool ShiftHack) { | 587 const Cfg *Func, bool ShiftHack) { |
588 if (!ALLOW_DUMP) | 588 if (!ALLOW_DUMP) |
589 return; | 589 return; |
590 Ostream &Str = Func->getContext()->getStrEmit(); | 590 Ostream &Str = Func->getContext()->getStrEmit(); |
591 assert(Inst->getSrcSize() == 2); | 591 assert(Inst->getSrcSize() == 2); |
592 Variable *Dest = Inst->getDest(); | 592 Variable *Dest = Inst->getDest(); |
593 assert(Dest == Inst->getSrc(0)); | 593 assert(Dest == Inst->getSrc(0)); |
594 Operand *Src1 = Inst->getSrc(1); | 594 Operand *Src1 = Inst->getSrc(1); |
595 Str << "\t" << Opcode << InstX8632::getWidthString(Dest->getType()) << "\t"; | 595 Str << "\t" << Opcode << InstX8632::getWidthString(Dest->getType()) << "\t"; |
596 const auto ShiftReg = llvm::dyn_cast<Variable>(Src1); | 596 const auto ShiftReg = llvm::dyn_cast<Variable>(Src1); |
597 if (ShiftHack && ShiftReg && ShiftReg->getRegNum() == RegX8632::Reg_ecx) | 597 if (ShiftHack && ShiftReg && ShiftReg->getRegNum() == RegX8632::Reg_ecx) |
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696 X8632::AssemblerX8632 *Asm = Func->getAssembler<X8632::AssemblerX8632>(); | 696 X8632::AssemblerX8632 *Asm = Func->getAssembler<X8632::AssemblerX8632>(); |
697 Op0Mem->emitSegmentOverride(Asm); | 697 Op0Mem->emitSegmentOverride(Asm); |
698 emitIASAddrOpTyGPR(Func, Ty, Op0Mem->toAsmAddress(Asm), Op1, Emitter); | 698 emitIASAddrOpTyGPR(Func, Ty, Op0Mem->toAsmAddress(Asm), Op1, Emitter); |
699 } else if (const auto Split = llvm::dyn_cast<VariableSplit>(Op0)) { | 699 } else if (const auto Split = llvm::dyn_cast<VariableSplit>(Op0)) { |
700 emitIASAddrOpTyGPR(Func, Ty, Split->toAsmAddress(Func), Op1, Emitter); | 700 emitIASAddrOpTyGPR(Func, Ty, Split->toAsmAddress(Func), Op1, Emitter); |
701 } else { | 701 } else { |
702 llvm_unreachable("Unexpected operand type"); | 702 llvm_unreachable("Unexpected operand type"); |
703 } | 703 } |
704 } | 704 } |
705 | 705 |
706 void emitIASGPRShift(const Cfg *Func, Type Ty, const Variable *Var, | 706 void InstX8632::emitIASGPRShift( |
707 const Operand *Src, | 707 const Cfg *Func, Type Ty, const Variable *Var, const Operand *Src, |
708 const X8632::AssemblerX8632::GPREmitterShiftOp &Emitter) { | 708 const X8632::AssemblerX8632::GPREmitterShiftOp &Emitter) { |
709 X8632::AssemblerX8632 *Asm = Func->getAssembler<X8632::AssemblerX8632>(); | 709 X8632::AssemblerX8632 *Asm = Func->getAssembler<X8632::AssemblerX8632>(); |
710 // Technically, the Dest Var can be mem as well, but we only use Reg. | 710 // Technically, the Dest Var can be mem as well, but we only use Reg. |
711 // We can extend this to check Dest if we decide to use that form. | 711 // We can extend this to check Dest if we decide to use that form. |
712 assert(Var->hasReg()); | 712 assert(Var->hasReg()); |
713 // We cheat a little and use GPRRegister even for byte operations. | 713 // We cheat a little and use GPRRegister even for byte operations. |
714 RegX8632::GPRRegister VarReg = | 714 RegX8632::GPRRegister VarReg = |
715 RegX8632::getEncodedByteRegOrGPR(Ty, Var->getRegNum()); | 715 RegX8632::getEncodedByteRegOrGPR(Ty, Var->getRegNum()); |
716 // Src must be reg == ECX or an Imm8. | 716 // Src must be reg == ECX or an Imm8. |
717 // This is asserted by the assembler. | 717 // This is asserted by the assembler. |
718 if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) { | 718 if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) { |
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3002 } | 3002 } |
3003 Str << "("; | 3003 Str << "("; |
3004 if (Func) | 3004 if (Func) |
3005 Var->dump(Func); | 3005 Var->dump(Func); |
3006 else | 3006 else |
3007 Var->dump(Str); | 3007 Var->dump(Str); |
3008 Str << ")"; | 3008 Str << ")"; |
3009 } | 3009 } |
3010 | 3010 |
3011 } // end of namespace Ice | 3011 } // end of namespace Ice |
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