Subzero ARM: do lowerIcmp, lowerBr, and a bit of lowerCall.

src/IceInstX8632.cpp

 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstX8632 and OperandX8632 classes,
@@ skipping 565 matching lines @@
     Str << " = ";
   }
   Str << "call ";
   getCallTarget()->dump(Func);
 }
 
 // The ShiftHack parameter is used to emit "cl" instead of "ecx" for
 // shift instructions, in order to be syntactically valid.  The
 // Opcode parameter needs to be char* and not IceString because of
 // template issues.
-void emitTwoAddress(const char *Opcode, const Inst *Inst, const Cfg *Func,
-                    bool ShiftHack) {
+void InstX8632::emitTwoAddress(const char *Opcode, const Inst *Inst,
+                               const Cfg *Func, bool ShiftHack) {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Inst->getSrcSize() == 2);
   Variable *Dest = Inst->getDest();
   assert(Dest == Inst->getSrc(0));
   Operand *Src1 = Inst->getSrc(1);
   Str << "\t" << Opcode << InstX8632::getWidthString(Dest->getType()) << "\t";
   const auto ShiftReg = llvm::dyn_cast<Variable>(Src1);
   if (ShiftHack && ShiftReg && ShiftReg->getRegNum() == RegX8632::Reg_ecx)
@@ skipping 98 matching lines @@
     X8632::AssemblerX8632 *Asm = Func->getAssembler<X8632::AssemblerX8632>();
     Op0Mem->emitSegmentOverride(Asm);
     emitIASAddrOpTyGPR(Func, Ty, Op0Mem->toAsmAddress(Asm), Op1, Emitter);
   } else if (const auto Split = llvm::dyn_cast<VariableSplit>(Op0)) {
     emitIASAddrOpTyGPR(Func, Ty, Split->toAsmAddress(Func), Op1, Emitter);
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
-void emitIASGPRShift(const Cfg *Func, Type Ty, const Variable *Var,
-                     const Operand *Src,
-                     const X8632::AssemblerX8632::GPREmitterShiftOp &Emitter) {
+void InstX8632::emitIASGPRShift(
+    const Cfg *Func, Type Ty, const Variable *Var, const Operand *Src,
+    const X8632::AssemblerX8632::GPREmitterShiftOp &Emitter) {
   X8632::AssemblerX8632 *Asm = Func->getAssembler<X8632::AssemblerX8632>();
   // Technically, the Dest Var can be mem as well, but we only use Reg.
   // We can extend this to check Dest if we decide to use that form.
   assert(Var->hasReg());
   // We cheat a little and use GPRRegister even for byte operations.
   RegX8632::GPRRegister VarReg =
       RegX8632::getEncodedByteRegOrGPR(Ty, Var->getRegNum());
   // Src must be reg == ECX or an Imm8.
   // This is asserted by the assembler.
   if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) {
@@ skipping 2283 matching lines @@
   }
   Str << "(";
   if (Func)
     Var->dump(Func);
   else
     Var->dump(Str);
   Str << ")";
 }
 
 } // end of namespace Ice