Subzero ARM: do lowerIcmp, lowerBr, and a bit of lowerCall.

src/IceInstARM32.def

 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines properties of ARM32 instructions in the form of x-macros.
@@ skipping 73 matching lines @@
 // Shifter types for Data-processing operands as defined in section A5.1.2.
 #define ICEINSTARM32SHIFT_TABLE                                         \
   /* enum value, emit */                                                \
   X(LSL, "lsl")                                                         \
   X(LSR, "lsr")                                                         \
   X(ASR, "asr")                                                         \
   X(ROR, "ror")                                                         \
   X(RRX, "rrx")                                                         \
 //#define X(tag, emit)
 
+// Attributes for the condition code 4-bit encoding (that is independent
+// of the APSR's NZCV fields). For example, EQ is 0, but corresponds to
+// Z = 1, and NE is 1, but corresponds to Z = 0.
+#define ICEINSTARM32COND_TABLE                                          \
+  /* enum value, encoding, opposite, emit */                            \
+  X(EQ, 0, NE, "eq") /* equal */                                        \
+  X(NE, 1, EQ, "ne") /* not equal */                                    \
+  X(CS, 2, CC, "cs") /* carry set/unsigned (AKA hs: higher or same) */  \
+  X(CC, 3, CS, "cc") /* carry clear/unsigned (AKA lo: lower) */         \
+  X(MI, 4, PL, "mi") /* minus/negative */                               \
+  X(PL, 5, MI, "pl") /* plus/positive or zero */                        \
+  X(VS, 6, VC, "vs") /* overflow (float unordered) */                   \
+  X(VC, 7, VS, "vc") /* no overflow (float not unordered) */            \
+  X(HI, 8, LS, "hi") /* unsigned higher */                              \
+  X(LS, 9, HI, "ls") /* unsigned lower or same */                       \
+  X(GE, 10, LT, "ge") /* signed greater than or equal */                \
+  X(LT, 11, GE, "lt") /* signed less than */                            \
+  X(GT, 12, LE, "gt") /* signed greater than */                         \
+  X(LE, 13, GT, "le") /* signed less than or equal */                   \
+  X(AL, 14, kNone, "") /* always (unconditional) */                     \
+  X(kNone, 15, kNone, "??") /* special condition / none */              \
+//#define(tag, encode, opp, emit)
+
 #endif // SUBZERO_SRC_ICEINSTARM32_DEF