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1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// | 1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file defines properties of ARM32 instructions in the form of x-macros. | 10 // This file defines properties of ARM32 instructions in the form of x-macros. |
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84 // Shifter types for Data-processing operands as defined in section A5.1.2. | 84 // Shifter types for Data-processing operands as defined in section A5.1.2. |
85 #define ICEINSTARM32SHIFT_TABLE \ | 85 #define ICEINSTARM32SHIFT_TABLE \ |
86 /* enum value, emit */ \ | 86 /* enum value, emit */ \ |
87 X(LSL, "lsl") \ | 87 X(LSL, "lsl") \ |
88 X(LSR, "lsr") \ | 88 X(LSR, "lsr") \ |
89 X(ASR, "asr") \ | 89 X(ASR, "asr") \ |
90 X(ROR, "ror") \ | 90 X(ROR, "ror") \ |
91 X(RRX, "rrx") \ | 91 X(RRX, "rrx") \ |
92 //#define X(tag, emit) | 92 //#define X(tag, emit) |
93 | 93 |
| 94 // Attributes for the condition code 4-bit encoding (that is independent |
| 95 // of the APSR's NZCV fields). For example, EQ is 0, but corresponds to |
| 96 // Z = 1, and NE is 1, but corresponds to Z = 0. |
| 97 #define ICEINSTARM32COND_TABLE \ |
| 98 /* enum value, encoding, opposite, emit */ \ |
| 99 X(EQ, 0, NE, "eq") /* equal */ \ |
| 100 X(NE, 1, EQ, "ne") /* not equal */ \ |
| 101 X(CS, 2, CC, "cs") /* carry set/unsigned (AKA hs: higher or same) */ \ |
| 102 X(CC, 3, CS, "cc") /* carry clear/unsigned (AKA lo: lower) */ \ |
| 103 X(MI, 4, PL, "mi") /* minus/negative */ \ |
| 104 X(PL, 5, MI, "pl") /* plus/positive or zero */ \ |
| 105 X(VS, 6, VC, "vs") /* overflow (float unordered) */ \ |
| 106 X(VC, 7, VS, "vc") /* no overflow (float not unordered) */ \ |
| 107 X(HI, 8, LS, "hi") /* unsigned higher */ \ |
| 108 X(LS, 9, HI, "ls") /* unsigned lower or same */ \ |
| 109 X(GE, 10, LT, "ge") /* signed greater than or equal */ \ |
| 110 X(LT, 11, GE, "lt") /* signed less than */ \ |
| 111 X(GT, 12, LE, "gt") /* signed greater than */ \ |
| 112 X(LE, 13, GT, "le") /* signed less than or equal */ \ |
| 113 X(AL, 14, kNone, "") /* always (unconditional) */ \ |
| 114 X(kNone, 15, kNone, "??") /* special condition / none */ \ |
| 115 //#define(tag, encode, opp, emit) |
| 116 |
94 #endif // SUBZERO_SRC_ICEINSTARM32_DEF | 117 #endif // SUBZERO_SRC_ICEINSTARM32_DEF |
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