Use R0/R1 instead of R4/R5 for eh_return on ARM

gcc/unwind-pnacl.h

Index: gcc/unwind-pnacl.h
diff --git a/gcc/unwind-pnacl.h b/gcc/unwind-pnacl.h
index 1d5ff86d6fc09d9f6798e9dbd510d80dc1292dc3..b52f0ed78533ef235f3b9a281b481a5569d2750a 100644
--- a/gcc/unwind-pnacl.h
+++ b/gcc/unwind-pnacl.h
@@ -94,7 +94,7 @@
 #elif defined(__i386__)
 #define pnacl_unwind_result0_reg() 0
 #elif defined(__arm__)
-#define pnacl_unwind_result0_reg() 4
+#define pnacl_unwind_result0_reg() 0
 #elif defined(__mips__)
 #define pnacl_unwind_result0_reg() 4
 #else

[jvoung (off chromium), 2015/06/03 17:21:04]

I wonder if mips is going to have the same problem...

[Derek Schuff, 2015/06/03 20:51:11]

Yeah, it seems likely. I still have the suspicion that there was something that
was kind of mitigating this problem before, that maybe isn't working now.
Because those registers were always getting clobbered before, and it seems kind
of inconceivable that there were never any situations where they were being used
until now.

@@ -107,7 +107,7 @@
 #elif defined(__i386__)
 #define pnacl_unwind_result1_reg() 2
 #elif defined(__arm__)
-#define pnacl_unwind_result1_reg() 5
+#define pnacl_unwind_result1_reg() 1
 #elif defined(__mips__)
 #define pnacl_unwind_result1_reg() 5
 #else