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Side by Side Diff: test/Transforms/NaCl/fix-vector-load-store-alignment.ll

Issue 1151093004: Changes from 3.7 merge to files not in upstream (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-llvm.git@master
Patch Set: Created 5 years, 7 months ago
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1 ; RUN: opt -fix-vector-load-store-alignment %s -S | FileCheck %s 1 ; RUN: opt -fix-vector-load-store-alignment %s -S | FileCheck %s
2 2
3 ; Test that vector load/store are always element-aligned when possible, and get 3 ; Test that vector load/store are always element-aligned when possible, and get
4 ; converted to scalar load/store when not. 4 ; converted to scalar load/store when not.
5 5
6 ; The datalayout is needed to determine the alignment of the load/stores. 6 ; The datalayout is needed to determine the alignment of the load/stores.
7 target datalayout = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64 :64:64-p:32:32:32-v128:32:32" 7 target datalayout = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64 :64:64-p:32:32:32-v128:32:32"
8 8
9 ; Load ========================================================================= 9 ; Load =========================================================================
10 10
11 define <4 x i1> @test_load_4xi1(<4 x i1>* %loc) { 11 define <4 x i1> @test_load_4xi1(<4 x i1>* %loc) {
12 ; CHECK-LABEL: test_load_4xi1 12 ; CHECK-LABEL: test_load_4xi1
13 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x i1>* %loc to i1* 13 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x i1>* %loc to i1*
14 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 0 14 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 0
15 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load i1* %[[GEP0]], align 4 15 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load i1, i1* %[[GEP0]], align 4
16 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <4 x i1> undef, i1 %[[LD0]], i3 2 0 16 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <4 x i1> undef, i1 %[[LD0]], i3 2 0
17 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 1 17 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 1
18 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load i1* %[[GEP1]], align 1 18 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load i1, i1* %[[GEP1]], align 1
19 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <4 x i1> %[[INS0]], i1 %[[LD1]] , i32 1 19 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <4 x i1> %[[INS0]], i1 %[[LD1]] , i32 1
20 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 2 20 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 2
21 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load i1* %[[GEP2]], align 2 21 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load i1, i1* %[[GEP2]], align 2
22 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <4 x i1> %[[INS1]], i1 %[[LD2]] , i32 2 22 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <4 x i1> %[[INS1]], i1 %[[LD2]] , i32 2
23 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 3 23 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 3
24 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load i1* %[[GEP3]], align 1 24 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load i1, i1* %[[GEP3]], align 1
25 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <4 x i1> %[[INS2]], i1 %[[LD3]] , i32 3 25 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <4 x i1> %[[INS2]], i1 %[[LD3]] , i32 3
26 ; CHECK-NEXT: ret <4 x i1> %[[INS3]] 26 ; CHECK-NEXT: ret <4 x i1> %[[INS3]]
27 %loaded = load <4 x i1>* %loc 27 %loaded = load <4 x i1>, <4 x i1>* %loc
28 ret <4 x i1> %loaded 28 ret <4 x i1> %loaded
29 } 29 }
30 30
31 define <8 x i1> @test_load_8xi1(<8 x i1>* %loc) { 31 define <8 x i1> @test_load_8xi1(<8 x i1>* %loc) {
32 ; CHECK-LABEL: test_load_8xi1 32 ; CHECK-LABEL: test_load_8xi1
33 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <8 x i1>* %loc to i1* 33 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <8 x i1>* %loc to i1*
34 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 0 34 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 0
35 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load i1* %[[GEP0]], align 8 35 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load i1, i1* %[[GEP0]], align 8
36 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <8 x i1> undef, i1 %[[LD0]], i3 2 0 36 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <8 x i1> undef, i1 %[[LD0]], i3 2 0
37 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 1 37 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 1
38 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load i1* %[[GEP1]], align 1 38 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load i1, i1* %[[GEP1]], align 1
39 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <8 x i1> %[[INS0]], i1 %[[LD1]] , i32 1 39 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <8 x i1> %[[INS0]], i1 %[[LD1]] , i32 1
40 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 2 40 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 2
41 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load i1* %[[GEP2]], align 2 41 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load i1, i1* %[[GEP2]], align 2
42 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <8 x i1> %[[INS1]], i1 %[[LD2]] , i32 2 42 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <8 x i1> %[[INS1]], i1 %[[LD2]] , i32 2
43 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 3 43 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 3
44 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load i1* %[[GEP3]], align 1 44 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load i1, i1* %[[GEP3]], align 1
45 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <8 x i1> %[[INS2]], i1 %[[LD3]] , i32 3 45 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <8 x i1> %[[INS2]], i1 %[[LD3]] , i32 3
46 ; CHECK-NEXT: %[[GEP4:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 4 46 ; CHECK-NEXT: %[[GEP4:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 4
47 ; CHECK-NEXT: %[[LD4:[0-9]+]] = load i1* %[[GEP4]], align 4 47 ; CHECK-NEXT: %[[LD4:[0-9]+]] = load i1, i1* %[[GEP4]], align 4
48 ; CHECK-NEXT: %[[INS4:[0-9]+]] = insertelement <8 x i1> %[[INS3]], i1 %[[LD4]] , i32 4 48 ; CHECK-NEXT: %[[INS4:[0-9]+]] = insertelement <8 x i1> %[[INS3]], i1 %[[LD4]] , i32 4
49 ; CHECK-NEXT: %[[GEP5:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 5 49 ; CHECK-NEXT: %[[GEP5:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 5
50 ; CHECK-NEXT: %[[LD5:[0-9]+]] = load i1* %[[GEP5]], align 1 50 ; CHECK-NEXT: %[[LD5:[0-9]+]] = load i1, i1* %[[GEP5]], align 1
51 ; CHECK-NEXT: %[[INS5:[0-9]+]] = insertelement <8 x i1> %[[INS4]], i1 %[[LD5]] , i32 5 51 ; CHECK-NEXT: %[[INS5:[0-9]+]] = insertelement <8 x i1> %[[INS4]], i1 %[[LD5]] , i32 5
52 ; CHECK-NEXT: %[[GEP6:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 6 52 ; CHECK-NEXT: %[[GEP6:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 6
53 ; CHECK-NEXT: %[[LD6:[0-9]+]] = load i1* %[[GEP6]], align 2 53 ; CHECK-NEXT: %[[LD6:[0-9]+]] = load i1, i1* %[[GEP6]], align 2
54 ; CHECK-NEXT: %[[INS6:[0-9]+]] = insertelement <8 x i1> %[[INS5]], i1 %[[LD6]] , i32 6 54 ; CHECK-NEXT: %[[INS6:[0-9]+]] = insertelement <8 x i1> %[[INS5]], i1 %[[LD6]] , i32 6
55 ; CHECK-NEXT: %[[GEP7:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 7 55 ; CHECK-NEXT: %[[GEP7:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 7
56 ; CHECK-NEXT: %[[LD7:[0-9]+]] = load i1* %[[GEP7]], align 1 56 ; CHECK-NEXT: %[[LD7:[0-9]+]] = load i1, i1* %[[GEP7]], align 1
57 ; CHECK-NEXT: %[[INS7:[0-9]+]] = insertelement <8 x i1> %[[INS6]], i1 %[[LD7]] , i32 7 57 ; CHECK-NEXT: %[[INS7:[0-9]+]] = insertelement <8 x i1> %[[INS6]], i1 %[[LD7]] , i32 7
58 ; CHECK-NEXT: ret <8 x i1> %[[INS7]] 58 ; CHECK-NEXT: ret <8 x i1> %[[INS7]]
59 %loaded = load <8 x i1>* %loc 59 %loaded = load <8 x i1>, <8 x i1>* %loc
60 ret <8 x i1> %loaded 60 ret <8 x i1> %loaded
61 } 61 }
62 62
63 define <16 x i1> @test_load_16xi1(<16 x i1>* %loc) { 63 define <16 x i1> @test_load_16xi1(<16 x i1>* %loc) {
64 ; CHECK-LABEL: test_load_16xi1 64 ; CHECK-LABEL: test_load_16xi1
65 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <16 x i1>* %loc to i1* 65 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <16 x i1>* %loc to i1*
66 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 0 66 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 0
67 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load i1* %[[GEP0]], align 16 67 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load i1, i1* %[[GEP0]], align 16
68 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <16 x i1> undef, i1 %[[LD0]], i 32 0 68 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <16 x i1> undef, i1 %[[LD0]], i 32 0
69 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 1 69 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 1
70 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load i1* %[[GEP1]], align 1 70 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load i1, i1* %[[GEP1]], align 1
71 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <16 x i1> %[[INS0]], i1 %[[LD1] ], i32 1 71 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <16 x i1> %[[INS0]], i1 %[[LD1] ], i32 1
72 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 2 72 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 2
73 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load i1* %[[GEP2]], align 2 73 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load i1, i1* %[[GEP2]], align 2
74 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <16 x i1> %[[INS1]], i1 %[[LD2] ], i32 2 74 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <16 x i1> %[[INS1]], i1 %[[LD2] ], i32 2
75 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 3 75 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 3
76 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load i1* %[[GEP3]], align 1 76 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load i1, i1* %[[GEP3]], align 1
77 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <16 x i1> %[[INS2]], i1 %[[LD3] ], i32 3 77 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <16 x i1> %[[INS2]], i1 %[[LD3] ], i32 3
78 ; CHECK-NEXT: %[[GEP4:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 4 78 ; CHECK-NEXT: %[[GEP4:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 4
79 ; CHECK-NEXT: %[[LD4:[0-9]+]] = load i1* %[[GEP4]], align 4 79 ; CHECK-NEXT: %[[LD4:[0-9]+]] = load i1, i1* %[[GEP4]], align 4
80 ; CHECK-NEXT: %[[INS4:[0-9]+]] = insertelement <16 x i1> %[[INS3]], i1 %[[LD4] ], i32 4 80 ; CHECK-NEXT: %[[INS4:[0-9]+]] = insertelement <16 x i1> %[[INS3]], i1 %[[LD4] ], i32 4
81 ; CHECK-NEXT: %[[GEP5:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 5 81 ; CHECK-NEXT: %[[GEP5:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 5
82 ; CHECK-NEXT: %[[LD5:[0-9]+]] = load i1* %[[GEP5]], align 1 82 ; CHECK-NEXT: %[[LD5:[0-9]+]] = load i1, i1* %[[GEP5]], align 1
83 ; CHECK-NEXT: %[[INS5:[0-9]+]] = insertelement <16 x i1> %[[INS4]], i1 %[[LD5] ], i32 5 83 ; CHECK-NEXT: %[[INS5:[0-9]+]] = insertelement <16 x i1> %[[INS4]], i1 %[[LD5] ], i32 5
84 ; CHECK-NEXT: %[[GEP6:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 6 84 ; CHECK-NEXT: %[[GEP6:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 6
85 ; CHECK-NEXT: %[[LD6:[0-9]+]] = load i1* %[[GEP6]], align 2 85 ; CHECK-NEXT: %[[LD6:[0-9]+]] = load i1, i1* %[[GEP6]], align 2
86 ; CHECK-NEXT: %[[INS6:[0-9]+]] = insertelement <16 x i1> %[[INS5]], i1 %[[LD6] ], i32 6 86 ; CHECK-NEXT: %[[INS6:[0-9]+]] = insertelement <16 x i1> %[[INS5]], i1 %[[LD6] ], i32 6
87 ; CHECK-NEXT: %[[GEP7:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 7 87 ; CHECK-NEXT: %[[GEP7:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 7
88 ; CHECK-NEXT: %[[LD7:[0-9]+]] = load i1* %[[GEP7]], align 1 88 ; CHECK-NEXT: %[[LD7:[0-9]+]] = load i1, i1* %[[GEP7]], align 1
89 ; CHECK-NEXT: %[[INS7:[0-9]+]] = insertelement <16 x i1> %[[INS6]], i1 %[[LD7] ], i32 7 89 ; CHECK-NEXT: %[[INS7:[0-9]+]] = insertelement <16 x i1> %[[INS6]], i1 %[[LD7] ], i32 7
90 ; CHECK-NEXT: %[[GEP8:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 8 90 ; CHECK-NEXT: %[[GEP8:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 8
91 ; CHECK-NEXT: %[[LD8:[0-9]+]] = load i1* %[[GEP8]], align 8 91 ; CHECK-NEXT: %[[LD8:[0-9]+]] = load i1, i1* %[[GEP8]], align 8
92 ; CHECK-NEXT: %[[INS8:[0-9]+]] = insertelement <16 x i1> %[[INS7]], i1 %[[LD8] ], i32 8 92 ; CHECK-NEXT: %[[INS8:[0-9]+]] = insertelement <16 x i1> %[[INS7]], i1 %[[LD8] ], i32 8
93 ; CHECK-NEXT: %[[GEP9:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 9 93 ; CHECK-NEXT: %[[GEP9:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 9
94 ; CHECK-NEXT: %[[LD9:[0-9]+]] = load i1* %[[GEP9]], align 1 94 ; CHECK-NEXT: %[[LD9:[0-9]+]] = load i1, i1* %[[GEP9]], align 1
95 ; CHECK-NEXT: %[[INS9:[0-9]+]] = insertelement <16 x i1> %[[INS8]], i1 %[[LD9] ], i32 9 95 ; CHECK-NEXT: %[[INS9:[0-9]+]] = insertelement <16 x i1> %[[INS8]], i1 %[[LD9] ], i32 9
96 ; CHECK-NEXT: %[[GEP10:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 10 96 ; CHECK-NEXT: %[[GEP10:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i3 2 10
97 ; CHECK-NEXT: %[[LD10:[0-9]+]] = load i1* %[[GEP10]], align 2 97 ; CHECK-NEXT: %[[LD10:[0-9]+]] = load i1, i1* %[[GEP10]], align 2
98 ; CHECK-NEXT: %[[INS10:[0-9]+]] = insertelement <16 x i1> %[[INS9]], i1 %[[LD1 0]], i32 10 98 ; CHECK-NEXT: %[[INS10:[0-9]+]] = insertelement <16 x i1> %[[INS9]], i1 %[[LD1 0]], i32 10
99 ; CHECK-NEXT: %[[GEP11:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 11 99 ; CHECK-NEXT: %[[GEP11:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i3 2 11
100 ; CHECK-NEXT: %[[LD11:[0-9]+]] = load i1* %[[GEP11]], align 1 100 ; CHECK-NEXT: %[[LD11:[0-9]+]] = load i1, i1* %[[GEP11]], align 1
101 ; CHECK-NEXT: %[[INS11:[0-9]+]] = insertelement <16 x i1> %[[INS10]], i1 %[[LD 11]], i32 11 101 ; CHECK-NEXT: %[[INS11:[0-9]+]] = insertelement <16 x i1> %[[INS10]], i1 %[[LD 11]], i32 11
102 ; CHECK-NEXT: %[[GEP12:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 12 102 ; CHECK-NEXT: %[[GEP12:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i3 2 12
103 ; CHECK-NEXT: %[[LD12:[0-9]+]] = load i1* %[[GEP12]], align 4 103 ; CHECK-NEXT: %[[LD12:[0-9]+]] = load i1, i1* %[[GEP12]], align 4
104 ; CHECK-NEXT: %[[INS12:[0-9]+]] = insertelement <16 x i1> %[[INS11]], i1 %[[LD 12]], i32 12 104 ; CHECK-NEXT: %[[INS12:[0-9]+]] = insertelement <16 x i1> %[[INS11]], i1 %[[LD 12]], i32 12
105 ; CHECK-NEXT: %[[GEP13:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 13 105 ; CHECK-NEXT: %[[GEP13:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i3 2 13
106 ; CHECK-NEXT: %[[LD13:[0-9]+]] = load i1* %[[GEP13]], align 1 106 ; CHECK-NEXT: %[[LD13:[0-9]+]] = load i1, i1* %[[GEP13]], align 1
107 ; CHECK-NEXT: %[[INS13:[0-9]+]] = insertelement <16 x i1> %[[INS12]], i1 %[[LD 13]], i32 13 107 ; CHECK-NEXT: %[[INS13:[0-9]+]] = insertelement <16 x i1> %[[INS12]], i1 %[[LD 13]], i32 13
108 ; CHECK-NEXT: %[[GEP14:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 14 108 ; CHECK-NEXT: %[[GEP14:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i3 2 14
109 ; CHECK-NEXT: %[[LD14:[0-9]+]] = load i1* %[[GEP14]], align 2 109 ; CHECK-NEXT: %[[LD14:[0-9]+]] = load i1, i1* %[[GEP14]], align 2
110 ; CHECK-NEXT: %[[INS14:[0-9]+]] = insertelement <16 x i1> %[[INS13]], i1 %[[LD 14]], i32 14 110 ; CHECK-NEXT: %[[INS14:[0-9]+]] = insertelement <16 x i1> %[[INS13]], i1 %[[LD 14]], i32 14
111 ; CHECK-NEXT: %[[GEP15:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 15 111 ; CHECK-NEXT: %[[GEP15:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i3 2 15
112 ; CHECK-NEXT: %[[LD15:[0-9]+]] = load i1* %[[GEP15]], align 1 112 ; CHECK-NEXT: %[[LD15:[0-9]+]] = load i1, i1* %[[GEP15]], align 1
113 ; CHECK-NEXT: %[[INS15:[0-9]+]] = insertelement <16 x i1> %[[INS14]], i1 %[[LD 15]], i32 15 113 ; CHECK-NEXT: %[[INS15:[0-9]+]] = insertelement <16 x i1> %[[INS14]], i1 %[[LD 15]], i32 15
114 ; CHECK-NEXT: ret <16 x i1> %[[INS15]] 114 ; CHECK-NEXT: ret <16 x i1> %[[INS15]]
115 %loaded = load <16 x i1>* %loc 115 %loaded = load <16 x i1>, <16 x i1>* %loc
116 ret <16 x i1> %loaded 116 ret <16 x i1> %loaded
117 } 117 }
118 118
119 define <4 x i32> @test_load_4xi32_align0(<4 x i32>* %loc) { 119 define <4 x i32> @test_load_4xi32_align0(<4 x i32>* %loc) {
120 ; CHECK-LABEL: test_load_4xi32_align0 120 ; CHECK-LABEL: test_load_4xi32_align0
121 ; CHECK-NEXT: %loaded = load <4 x i32>* %loc, align 4 121 ; CHECK-NEXT: %loaded = load <4 x i32>, <4 x i32>* %loc, align 4
122 ; CHECK-NEXT: ret <4 x i32> %loaded 122 ; CHECK-NEXT: ret <4 x i32> %loaded
123 %loaded = load <4 x i32>* %loc 123 %loaded = load <4 x i32>, <4 x i32>* %loc
124 ret <4 x i32> %loaded 124 ret <4 x i32> %loaded
125 } 125 }
126 126
127 define <4 x i32> @test_load_4xi32_align1(<4 x i32>* %loc) { 127 define <4 x i32> @test_load_4xi32_align1(<4 x i32>* %loc) {
128 ; CHECK-LABEL: test_load_4xi32_align1 128 ; CHECK-LABEL: test_load_4xi32_align1
129 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x i32>* %loc to i32* 129 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x i32>* %loc to i32*
130 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 0 130 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 0
131 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load i32* %[[GEP0]], align 1 131 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load i32, i32* %[[GEP0]], align 1
132 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <4 x i32> undef, i32 %[[LD0]], i32 0 132 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <4 x i32> undef, i32 %[[LD0]], i32 0
133 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 1 133 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 1
134 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load i32* %[[GEP1]], align 1 134 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load i32, i32* %[[GEP1]], align 1
135 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <4 x i32> %[[INS0]], i32 %[[LD1 ]], i32 1 135 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <4 x i32> %[[INS0]], i32 %[[LD1 ]], i32 1
136 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 2 136 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 2
137 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load i32* %[[GEP2]], align 1 137 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load i32, i32* %[[GEP2]], align 1
138 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <4 x i32> %[[INS1]], i32 %[[LD2 ]], i32 2 138 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <4 x i32> %[[INS1]], i32 %[[LD2 ]], i32 2
139 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 3 139 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 3
140 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load i32* %[[GEP3]], align 1 140 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load i32, i32* %[[GEP3]], align 1
141 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <4 x i32> %[[INS2]], i32 %[[LD3 ]], i32 3 141 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <4 x i32> %[[INS2]], i32 %[[LD3 ]], i32 3
142 ; CHECK-NEXT: ret <4 x i32> %[[INS3]] 142 ; CHECK-NEXT: ret <4 x i32> %[[INS3]]
143 %loaded = load <4 x i32>* %loc, align 1 143 %loaded = load <4 x i32>, <4 x i32>* %loc, align 1
144 ret <4 x i32> %loaded 144 ret <4 x i32> %loaded
145 } 145 }
146 146
147 define <4 x i32> @test_load_4xi32_align2(<4 x i32>* %loc) { 147 define <4 x i32> @test_load_4xi32_align2(<4 x i32>* %loc) {
148 ; CHECK-LABEL: test_load_4xi32_align2 148 ; CHECK-LABEL: test_load_4xi32_align2
149 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x i32>* %loc to i32* 149 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x i32>* %loc to i32*
150 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 0 150 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 0
151 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load i32* %[[GEP0]], align 2 151 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load i32, i32* %[[GEP0]], align 2
152 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <4 x i32> undef, i32 %[[LD0]], i32 0 152 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <4 x i32> undef, i32 %[[LD0]], i32 0
153 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 1 153 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 1
154 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load i32* %[[GEP1]], align 2 154 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load i32, i32* %[[GEP1]], align 2
155 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <4 x i32> %[[INS0]], i32 %[[LD1 ]], i32 1 155 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <4 x i32> %[[INS0]], i32 %[[LD1 ]], i32 1
156 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 2 156 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 2
157 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load i32* %[[GEP2]], align 2 157 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load i32, i32* %[[GEP2]], align 2
158 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <4 x i32> %[[INS1]], i32 %[[LD2 ]], i32 2 158 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <4 x i32> %[[INS1]], i32 %[[LD2 ]], i32 2
159 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 3 159 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 3
160 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load i32* %[[GEP3]], align 2 160 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load i32, i32* %[[GEP3]], align 2
161 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <4 x i32> %[[INS2]], i32 %[[LD3 ]], i32 3 161 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <4 x i32> %[[INS2]], i32 %[[LD3 ]], i32 3
162 ; CHECK-NEXT: ret <4 x i32> %[[INS3]] 162 ; CHECK-NEXT: ret <4 x i32> %[[INS3]]
163 %loaded = load <4 x i32>* %loc, align 2 163 %loaded = load <4 x i32>, <4 x i32>* %loc, align 2
164 ret <4 x i32> %loaded 164 ret <4 x i32> %loaded
165 } 165 }
166 166
167 define <4 x i32> @test_load_4xi32_align4(<4 x i32>* %loc) { 167 define <4 x i32> @test_load_4xi32_align4(<4 x i32>* %loc) {
168 ; CHECK-LABEL: test_load_4xi32_align4 168 ; CHECK-LABEL: test_load_4xi32_align4
169 ; CHECK-NEXT: %loaded = load <4 x i32>* %loc, align 4 169 ; CHECK-NEXT: %loaded = load <4 x i32>, <4 x i32>* %loc, align 4
170 ; CHECK-NEXT: ret <4 x i32> %loaded 170 ; CHECK-NEXT: ret <4 x i32> %loaded
171 %loaded = load <4 x i32>* %loc, align 4 171 %loaded = load <4 x i32>, <4 x i32>* %loc, align 4
172 ret <4 x i32> %loaded 172 ret <4 x i32> %loaded
173 } 173 }
174 174
175 define <4 x i32> @test_load_4xi32_align8(<4 x i32>* %loc) { 175 define <4 x i32> @test_load_4xi32_align8(<4 x i32>* %loc) {
176 ; CHECK-LABEL: test_load_4xi32_align8 176 ; CHECK-LABEL: test_load_4xi32_align8
177 ; CHECK-NEXT: %loaded = load <4 x i32>* %loc, align 4 177 ; CHECK-NEXT: %loaded = load <4 x i32>, <4 x i32>* %loc, align 4
178 ; CHECK-NEXT: ret <4 x i32> %loaded 178 ; CHECK-NEXT: ret <4 x i32> %loaded
179 %loaded = load <4 x i32>* %loc, align 8 179 %loaded = load <4 x i32>, <4 x i32>* %loc, align 8
180 ret <4 x i32> %loaded 180 ret <4 x i32> %loaded
181 } 181 }
182 182
183 define <4 x i32> @test_load_4xi32_align16(<4 x i32>* %loc) { 183 define <4 x i32> @test_load_4xi32_align16(<4 x i32>* %loc) {
184 ; CHECK-LABEL: test_load_4xi32_align16 184 ; CHECK-LABEL: test_load_4xi32_align16
185 ; CHECK-NEXT: %loaded = load <4 x i32>* %loc, align 4 185 ; CHECK-NEXT: %loaded = load <4 x i32>, <4 x i32>* %loc, align 4
186 ; CHECK-NEXT: ret <4 x i32> %loaded 186 ; CHECK-NEXT: ret <4 x i32> %loaded
187 %loaded = load <4 x i32>* %loc, align 16 187 %loaded = load <4 x i32>, <4 x i32>* %loc, align 16
188 ret <4 x i32> %loaded 188 ret <4 x i32> %loaded
189 } 189 }
190 190
191 define <4 x i32> @test_load_4xi32_align32(<4 x i32>* %loc) { 191 define <4 x i32> @test_load_4xi32_align32(<4 x i32>* %loc) {
192 ; CHECK-LABEL: test_load_4xi32_align32 192 ; CHECK-LABEL: test_load_4xi32_align32
193 ; CHECK-NEXT: %loaded = load <4 x i32>* %loc, align 4 193 ; CHECK-NEXT: %loaded = load <4 x i32>, <4 x i32>* %loc, align 4
194 ; CHECK-NEXT: ret <4 x i32> %loaded 194 ; CHECK-NEXT: ret <4 x i32> %loaded
195 %loaded = load <4 x i32>* %loc, align 32 195 %loaded = load <4 x i32>, <4 x i32>* %loc, align 32
196 ret <4 x i32> %loaded 196 ret <4 x i32> %loaded
197 } 197 }
198 198
199 define <4 x float> @test_load_4xfloat_align0(<4 x float>* %loc) { 199 define <4 x float> @test_load_4xfloat_align0(<4 x float>* %loc) {
200 ; CHECK-LABEL: test_load_4xfloat_align0 200 ; CHECK-LABEL: test_load_4xfloat_align0
201 ; CHECK-NEXT: %loaded = load <4 x float>* %loc, align 4 201 ; CHECK-NEXT: %loaded = load <4 x float>, <4 x float>* %loc, align 4
202 ; CHECK-NEXT: ret <4 x float> %loaded 202 ; CHECK-NEXT: ret <4 x float> %loaded
203 %loaded = load <4 x float>* %loc 203 %loaded = load <4 x float>, <4 x float>* %loc
204 ret <4 x float> %loaded 204 ret <4 x float> %loaded
205 } 205 }
206 206
207 define <4 x float> @test_load_4xfloat_align2(<4 x float>* %loc) { 207 define <4 x float> @test_load_4xfloat_align2(<4 x float>* %loc) {
208 ; CHECK-LABEL: test_load_4xfloat_align2 208 ; CHECK-LABEL: test_load_4xfloat_align2
209 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x float>* %loc to float* 209 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x float>* %loc to float*
210 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds float* %[[BASE]], i32 0 210 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds float, float* %[[BASE] ], i32 0
211 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load float* %[[GEP0]], align 2 211 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load float, float* %[[GEP0]], align 2
212 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <4 x float> undef, float %[[LD0 ]], i32 0 212 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <4 x float> undef, float %[[LD0 ]], i32 0
213 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds float* %[[BASE]], i32 1 213 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds float, float* %[[BASE] ], i32 1
214 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load float* %[[GEP1]], align 2 214 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load float, float* %[[GEP1]], align 2
215 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <4 x float> %[[INS0]], float %[ [LD1]], i32 1 215 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <4 x float> %[[INS0]], float %[ [LD1]], i32 1
216 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds float* %[[BASE]], i32 2 216 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds float, float* %[[BASE] ], i32 2
217 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load float* %[[GEP2]], align 2 217 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load float, float* %[[GEP2]], align 2
218 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <4 x float> %[[INS1]], float %[ [LD2]], i32 2 218 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <4 x float> %[[INS1]], float %[ [LD2]], i32 2
219 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds float* %[[BASE]], i32 3 219 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds float, float* %[[BASE] ], i32 3
220 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load float* %[[GEP3]], align 2 220 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load float, float* %[[GEP3]], align 2
221 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <4 x float> %[[INS2]], float %[ [LD3]], i32 3 221 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <4 x float> %[[INS2]], float %[ [LD3]], i32 3
222 ; CHECK-NEXT: ret <4 x float> %[[INS3]] 222 ; CHECK-NEXT: ret <4 x float> %[[INS3]]
223 %loaded = load <4 x float>* %loc, align 2 223 %loaded = load <4 x float>, <4 x float>* %loc, align 2
224 ret <4 x float> %loaded 224 ret <4 x float> %loaded
225 } 225 }
226 226
227 define <4 x float> @test_load_4xfloat_align4(<4 x float>* %loc) { 227 define <4 x float> @test_load_4xfloat_align4(<4 x float>* %loc) {
228 ; CHECK-LABEL: test_load_4xfloat_align4 228 ; CHECK-LABEL: test_load_4xfloat_align4
229 ; CHECK-NEXT: %loaded = load <4 x float>* %loc, align 4 229 ; CHECK-NEXT: %loaded = load <4 x float>, <4 x float>* %loc, align 4
230 ; CHECK-NEXT: ret <4 x float> %loaded 230 ; CHECK-NEXT: ret <4 x float> %loaded
231 %loaded = load <4 x float>* %loc, align 4 231 %loaded = load <4 x float>, <4 x float>* %loc, align 4
232 ret <4 x float> %loaded 232 ret <4 x float> %loaded
233 } 233 }
234 234
235 define <8 x i16> @test_load_8xi16_align0(<8 x i16>* %loc) { 235 define <8 x i16> @test_load_8xi16_align0(<8 x i16>* %loc) {
236 ; CHECK-LABEL: test_load_8xi16_align0 236 ; CHECK-LABEL: test_load_8xi16_align0
237 ; CHECK-NEXT: %loaded = load <8 x i16>* %loc, align 2 237 ; CHECK-NEXT: %loaded = load <8 x i16>, <8 x i16>* %loc, align 2
238 ; CHECK-NEXT: ret <8 x i16> %loaded 238 ; CHECK-NEXT: ret <8 x i16> %loaded
239 %loaded = load <8 x i16>* %loc 239 %loaded = load <8 x i16>, <8 x i16>* %loc
240 ret <8 x i16> %loaded 240 ret <8 x i16> %loaded
241 } 241 }
242 242
243 define <8 x i16> @test_load_8xi16_align1(<8 x i16>* %loc) { 243 define <8 x i16> @test_load_8xi16_align1(<8 x i16>* %loc) {
244 ; CHECK-LABEL: test_load_8xi16_align1 244 ; CHECK-LABEL: test_load_8xi16_align1
245 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <8 x i16>* %loc to i16* 245 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <8 x i16>* %loc to i16*
246 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i16* %[[BASE]], i32 0 246 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i16, i16* %[[BASE]], i 32 0
247 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load i16* %[[GEP0]], align 1 247 ; CHECK-NEXT: %[[LD0:[0-9]+]] = load i16, i16* %[[GEP0]], align 1
248 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <8 x i16> undef, i16 %[[LD0]], i32 0 248 ; CHECK-NEXT: %[[INS0:[0-9]+]] = insertelement <8 x i16> undef, i16 %[[LD0]], i32 0
249 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i16* %[[BASE]], i32 1 249 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i16, i16* %[[BASE]], i 32 1
250 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load i16* %[[GEP1]], align 1 250 ; CHECK-NEXT: %[[LD1:[0-9]+]] = load i16, i16* %[[GEP1]], align 1
251 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <8 x i16> %[[INS0]], i16 %[[LD1 ]], i32 1 251 ; CHECK-NEXT: %[[INS1:[0-9]+]] = insertelement <8 x i16> %[[INS0]], i16 %[[LD1 ]], i32 1
252 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i16* %[[BASE]], i32 2 252 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i16, i16* %[[BASE]], i 32 2
253 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load i16* %[[GEP2]], align 1 253 ; CHECK-NEXT: %[[LD2:[0-9]+]] = load i16, i16* %[[GEP2]], align 1
254 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <8 x i16> %[[INS1]], i16 %[[LD2 ]], i32 2 254 ; CHECK-NEXT: %[[INS2:[0-9]+]] = insertelement <8 x i16> %[[INS1]], i16 %[[LD2 ]], i32 2
255 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i16* %[[BASE]], i32 3 255 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i16, i16* %[[BASE]], i 32 3
256 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load i16* %[[GEP3]], align 1 256 ; CHECK-NEXT: %[[LD3:[0-9]+]] = load i16, i16* %[[GEP3]], align 1
257 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <8 x i16> %[[INS2]], i16 %[[LD3 ]], i32 3 257 ; CHECK-NEXT: %[[INS3:[0-9]+]] = insertelement <8 x i16> %[[INS2]], i16 %[[LD3 ]], i32 3
258 ; CHECK-NEXT: %[[GEP4:[0-9]+]] = getelementptr inbounds i16* %[[BASE]], i32 4 258 ; CHECK-NEXT: %[[GEP4:[0-9]+]] = getelementptr inbounds i16, i16* %[[BASE]], i 32 4
259 ; CHECK-NEXT: %[[LD4:[0-9]+]] = load i16* %[[GEP4]], align 1 259 ; CHECK-NEXT: %[[LD4:[0-9]+]] = load i16, i16* %[[GEP4]], align 1
260 ; CHECK-NEXT: %[[INS4:[0-9]+]] = insertelement <8 x i16> %[[INS3]], i16 %[[LD4 ]], i32 4 260 ; CHECK-NEXT: %[[INS4:[0-9]+]] = insertelement <8 x i16> %[[INS3]], i16 %[[LD4 ]], i32 4
261 ; CHECK-NEXT: %[[GEP5:[0-9]+]] = getelementptr inbounds i16* %[[BASE]], i32 5 261 ; CHECK-NEXT: %[[GEP5:[0-9]+]] = getelementptr inbounds i16, i16* %[[BASE]], i 32 5
262 ; CHECK-NEXT: %[[LD5:[0-9]+]] = load i16* %[[GEP5]], align 1 262 ; CHECK-NEXT: %[[LD5:[0-9]+]] = load i16, i16* %[[GEP5]], align 1
263 ; CHECK-NEXT: %[[INS5:[0-9]+]] = insertelement <8 x i16> %[[INS4]], i16 %[[LD5 ]], i32 5 263 ; CHECK-NEXT: %[[INS5:[0-9]+]] = insertelement <8 x i16> %[[INS4]], i16 %[[LD5 ]], i32 5
264 ; CHECK-NEXT: %[[GEP6:[0-9]+]] = getelementptr inbounds i16* %[[BASE]], i32 6 264 ; CHECK-NEXT: %[[GEP6:[0-9]+]] = getelementptr inbounds i16, i16* %[[BASE]], i 32 6
265 ; CHECK-NEXT: %[[LD6:[0-9]+]] = load i16* %[[GEP6]], align 1 265 ; CHECK-NEXT: %[[LD6:[0-9]+]] = load i16, i16* %[[GEP6]], align 1
266 ; CHECK-NEXT: %[[INS6:[0-9]+]] = insertelement <8 x i16> %[[INS5]], i16 %[[LD6 ]], i32 6 266 ; CHECK-NEXT: %[[INS6:[0-9]+]] = insertelement <8 x i16> %[[INS5]], i16 %[[LD6 ]], i32 6
267 ; CHECK-NEXT: %[[GEP7:[0-9]+]] = getelementptr inbounds i16* %[[BASE]], i32 7 267 ; CHECK-NEXT: %[[GEP7:[0-9]+]] = getelementptr inbounds i16, i16* %[[BASE]], i 32 7
268 ; CHECK-NEXT: %[[LD7:[0-9]+]] = load i16* %[[GEP7]], align 1 268 ; CHECK-NEXT: %[[LD7:[0-9]+]] = load i16, i16* %[[GEP7]], align 1
269 ; CHECK-NEXT: %[[INS7:[0-9]+]] = insertelement <8 x i16> %[[INS6]], i16 %[[LD7 ]], i32 7 269 ; CHECK-NEXT: %[[INS7:[0-9]+]] = insertelement <8 x i16> %[[INS6]], i16 %[[LD7 ]], i32 7
270 ; CHECK-NEXT: ret <8 x i16> %[[INS7]] 270 ; CHECK-NEXT: ret <8 x i16> %[[INS7]]
271 %loaded = load <8 x i16>* %loc, align 1 271 %loaded = load <8 x i16>, <8 x i16>* %loc, align 1
272 ret <8 x i16> %loaded 272 ret <8 x i16> %loaded
273 } 273 }
274 274
275 define <8 x i16> @test_load_8xi16_align2(<8 x i16>* %loc) { 275 define <8 x i16> @test_load_8xi16_align2(<8 x i16>* %loc) {
276 ; CHECK-LABEL: test_load_8xi16_align2 276 ; CHECK-LABEL: test_load_8xi16_align2
277 ; CHECK-NEXT: %loaded = load <8 x i16>* %loc, align 2 277 ; CHECK-NEXT: %loaded = load <8 x i16>, <8 x i16>* %loc, align 2
278 ; CHECK-NEXT: ret <8 x i16> %loaded 278 ; CHECK-NEXT: ret <8 x i16> %loaded
279 %loaded = load <8 x i16>* %loc, align 2 279 %loaded = load <8 x i16>, <8 x i16>* %loc, align 2
280 ret <8 x i16> %loaded 280 ret <8 x i16> %loaded
281 } 281 }
282 282
283 define <16 x i8> @test_load_16xi8_align0(<16 x i8>* %loc) { 283 define <16 x i8> @test_load_16xi8_align0(<16 x i8>* %loc) {
284 ; CHECK-LABEL: test_load_16xi8_align0 284 ; CHECK-LABEL: test_load_16xi8_align0
285 ; CHECK-NEXT: %loaded = load <16 x i8>* %loc, align 1 285 ; CHECK-NEXT: %loaded = load <16 x i8>, <16 x i8>* %loc, align 1
286 ; CHECK-NEXT: ret <16 x i8> %loaded 286 ; CHECK-NEXT: ret <16 x i8> %loaded
287 %loaded = load <16 x i8>* %loc 287 %loaded = load <16 x i8>, <16 x i8>* %loc
288 ret <16 x i8> %loaded 288 ret <16 x i8> %loaded
289 } 289 }
290 290
291 define <16 x i8> @test_load_16xi8_align1(<16 x i8>* %loc) { 291 define <16 x i8> @test_load_16xi8_align1(<16 x i8>* %loc) {
292 ; CHECK-LABEL: test_load_16xi8_align1 292 ; CHECK-LABEL: test_load_16xi8_align1
293 ; CHECK-NEXT: %loaded = load <16 x i8>* %loc, align 1 293 ; CHECK-NEXT: %loaded = load <16 x i8>, <16 x i8>* %loc, align 1
294 ; CHECK-NEXT: ret <16 x i8> %loaded 294 ; CHECK-NEXT: ret <16 x i8> %loaded
295 %loaded = load <16 x i8>* %loc, align 1 295 %loaded = load <16 x i8>, <16 x i8>* %loc, align 1
296 ret <16 x i8> %loaded 296 ret <16 x i8> %loaded
297 } 297 }
298 298
299 299
300 ; Store ======================================================================== 300 ; Store ========================================================================
301 301
302 define void @test_store_4xi1(<4 x i1> %val, <4 x i1>* %loc) { 302 define void @test_store_4xi1(<4 x i1> %val, <4 x i1>* %loc) {
303 ; CHECK-LABEL: test_store_4xi1 303 ; CHECK-LABEL: test_store_4xi1
304 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x i1>* %loc to i1* 304 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x i1>* %loc to i1*
305 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 0 305 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 0
306 ; CHECK-NEXT: %[[EXT0:[0-9]+]] = extractelement <4 x i1> %val, i32 0 306 ; CHECK-NEXT: %[[EXT0:[0-9]+]] = extractelement <4 x i1> %val, i32 0
307 ; CHECK-NEXT: store i1 %[[EXT0]], i1* %[[GEP0]], align 4 307 ; CHECK-NEXT: store i1 %[[EXT0]], i1* %[[GEP0]], align 4
308 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 1 308 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 1
309 ; CHECK-NEXT: %[[EXT1:[0-9]+]] = extractelement <4 x i1> %val, i32 1 309 ; CHECK-NEXT: %[[EXT1:[0-9]+]] = extractelement <4 x i1> %val, i32 1
310 ; CHECK-NEXT: store i1 %[[EXT1]], i1* %[[GEP1]], align 1 310 ; CHECK-NEXT: store i1 %[[EXT1]], i1* %[[GEP1]], align 1
311 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 2 311 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 2
312 ; CHECK-NEXT: %[[EXT2:[0-9]+]] = extractelement <4 x i1> %val, i32 2 312 ; CHECK-NEXT: %[[EXT2:[0-9]+]] = extractelement <4 x i1> %val, i32 2
313 ; CHECK-NEXT: store i1 %[[EXT2]], i1* %[[GEP2]], align 2 313 ; CHECK-NEXT: store i1 %[[EXT2]], i1* %[[GEP2]], align 2
314 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i1* %[[BASE]], i32 3 314 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i1, i1* %[[BASE]], i32 3
315 ; CHECK-NEXT: %[[EXT3:[0-9]+]] = extractelement <4 x i1> %val, i32 3 315 ; CHECK-NEXT: %[[EXT3:[0-9]+]] = extractelement <4 x i1> %val, i32 3
316 ; CHECK-NEXT: store i1 %[[EXT3]], i1* %[[GEP3]], align 1 316 ; CHECK-NEXT: store i1 %[[EXT3]], i1* %[[GEP3]], align 1
317 ; CHECK-NEXT: ret void 317 ; CHECK-NEXT: ret void
318 store <4 x i1> %val, <4 x i1>* %loc 318 store <4 x i1> %val, <4 x i1>* %loc
319 ret void 319 ret void
320 } 320 }
321 321
322 define void @test_store_4xi32_align0(<4 x i32> %val, <4 x i32>* %loc) { 322 define void @test_store_4xi32_align0(<4 x i32> %val, <4 x i32>* %loc) {
323 ; CHECK-LABEL: test_store_4xi32_align0 323 ; CHECK-LABEL: test_store_4xi32_align0
324 ; CHECK-NEXT: store <4 x i32> %val, <4 x i32>* %loc, align 4 324 ; CHECK-NEXT: store <4 x i32> %val, <4 x i32>* %loc, align 4
325 ; CHECK-NEXT: ret void 325 ; CHECK-NEXT: ret void
326 store <4 x i32> %val, <4 x i32>* %loc 326 store <4 x i32> %val, <4 x i32>* %loc
327 ret void 327 ret void
328 } 328 }
329 329
330 define void @test_store_4xi32_align1(<4 x i32> %val, <4 x i32>* %loc) { 330 define void @test_store_4xi32_align1(<4 x i32> %val, <4 x i32>* %loc) {
331 ; CHECK-LABEL: test_store_4xi32_align1 331 ; CHECK-LABEL: test_store_4xi32_align1
332 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x i32>* %loc to i32* 332 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x i32>* %loc to i32*
333 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 0 333 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 0
334 ; CHECK-NEXT: %[[EXT0:[0-9]+]] = extractelement <4 x i32> %val, i32 0 334 ; CHECK-NEXT: %[[EXT0:[0-9]+]] = extractelement <4 x i32> %val, i32 0
335 ; CHECK-NEXT: store i32 %[[EXT0]], i32* %[[GEP0]], align 1 335 ; CHECK-NEXT: store i32 %[[EXT0]], i32* %[[GEP0]], align 1
336 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 1 336 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 1
337 ; CHECK-NEXT: %[[EXT1:[0-9]+]] = extractelement <4 x i32> %val, i32 1 337 ; CHECK-NEXT: %[[EXT1:[0-9]+]] = extractelement <4 x i32> %val, i32 1
338 ; CHECK-NEXT: store i32 %[[EXT1]], i32* %[[GEP1]], align 1 338 ; CHECK-NEXT: store i32 %[[EXT1]], i32* %[[GEP1]], align 1
339 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 2 339 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 2
340 ; CHECK-NEXT: %[[EXT2:[0-9]+]] = extractelement <4 x i32> %val, i32 2 340 ; CHECK-NEXT: %[[EXT2:[0-9]+]] = extractelement <4 x i32> %val, i32 2
341 ; CHECK-NEXT: store i32 %[[EXT2]], i32* %[[GEP2]], align 1 341 ; CHECK-NEXT: store i32 %[[EXT2]], i32* %[[GEP2]], align 1
342 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 3 342 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 3
343 ; CHECK-NEXT: %[[EXT3:[0-9]+]] = extractelement <4 x i32> %val, i32 3 343 ; CHECK-NEXT: %[[EXT3:[0-9]+]] = extractelement <4 x i32> %val, i32 3
344 ; CHECK-NEXT: store i32 %[[EXT3]], i32* %[[GEP3]], align 1 344 ; CHECK-NEXT: store i32 %[[EXT3]], i32* %[[GEP3]], align 1
345 ; CHECK-NEXT: ret void 345 ; CHECK-NEXT: ret void
346 store <4 x i32> %val, <4 x i32>* %loc, align 1 346 store <4 x i32> %val, <4 x i32>* %loc, align 1
347 ret void 347 ret void
348 } 348 }
349 349
350 define void @test_store_4xi32_align2(<4 x i32> %val, <4 x i32>* %loc) { 350 define void @test_store_4xi32_align2(<4 x i32> %val, <4 x i32>* %loc) {
351 ; CHECK-LABEL: test_store_4xi32_align2 351 ; CHECK-LABEL: test_store_4xi32_align2
352 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x i32>* %loc to i32* 352 ; CHECK-NEXT: %[[BASE:[0-9]+]] = bitcast <4 x i32>* %loc to i32*
353 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 0 353 ; CHECK-NEXT: %[[GEP0:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 0
354 ; CHECK-NEXT: %[[EXT0:[0-9]+]] = extractelement <4 x i32> %val, i32 0 354 ; CHECK-NEXT: %[[EXT0:[0-9]+]] = extractelement <4 x i32> %val, i32 0
355 ; CHECK-NEXT: store i32 %[[EXT0]], i32* %[[GEP0]], align 2 355 ; CHECK-NEXT: store i32 %[[EXT0]], i32* %[[GEP0]], align 2
356 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 1 356 ; CHECK-NEXT: %[[GEP1:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 1
357 ; CHECK-NEXT: %[[EXT1:[0-9]+]] = extractelement <4 x i32> %val, i32 1 357 ; CHECK-NEXT: %[[EXT1:[0-9]+]] = extractelement <4 x i32> %val, i32 1
358 ; CHECK-NEXT: store i32 %[[EXT1]], i32* %[[GEP1]], align 2 358 ; CHECK-NEXT: store i32 %[[EXT1]], i32* %[[GEP1]], align 2
359 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 2 359 ; CHECK-NEXT: %[[GEP2:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 2
360 ; CHECK-NEXT: %[[EXT2:[0-9]+]] = extractelement <4 x i32> %val, i32 2 360 ; CHECK-NEXT: %[[EXT2:[0-9]+]] = extractelement <4 x i32> %val, i32 2
361 ; CHECK-NEXT: store i32 %[[EXT2]], i32* %[[GEP2]], align 2 361 ; CHECK-NEXT: store i32 %[[EXT2]], i32* %[[GEP2]], align 2
362 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i32* %[[BASE]], i32 3 362 ; CHECK-NEXT: %[[GEP3:[0-9]+]] = getelementptr inbounds i32, i32* %[[BASE]], i 32 3
363 ; CHECK-NEXT: %[[EXT3:[0-9]+]] = extractelement <4 x i32> %val, i32 3 363 ; CHECK-NEXT: %[[EXT3:[0-9]+]] = extractelement <4 x i32> %val, i32 3
364 ; CHECK-NEXT: store i32 %[[EXT3]], i32* %[[GEP3]], align 2 364 ; CHECK-NEXT: store i32 %[[EXT3]], i32* %[[GEP3]], align 2
365 ; CHECK-NEXT: ret void 365 ; CHECK-NEXT: ret void
366 store <4 x i32> %val, <4 x i32>* %loc, align 2 366 store <4 x i32> %val, <4 x i32>* %loc, align 2
367 ret void 367 ret void
368 } 368 }
369 369
370 define void @test_store_4xi32_align4(<4 x i32> %val, <4 x i32>* %loc) { 370 define void @test_store_4xi32_align4(<4 x i32> %val, <4 x i32>* %loc) {
371 ; CHECK-LABEL: test_store_4xi32_align4 371 ; CHECK-LABEL: test_store_4xi32_align4
372 ; CHECK-NEXT: store <4 x i32> %val, <4 x i32>* %loc, align 4 372 ; CHECK-NEXT: store <4 x i32> %val, <4 x i32>* %loc, align 4
(...skipping 32 matching lines...) Expand 10 before | Expand all | Expand 10 after
405 ; CHECK-NEXT: ret void 405 ; CHECK-NEXT: ret void
406 store <4 x float> %val, <4 x float>* %loc 406 store <4 x float> %val, <4 x float>* %loc
407 ret void 407 ret void
408 } 408 }
409 409
410 410
411 ; Volatile ===================================================================== 411 ; Volatile =====================================================================
412 412
413 define <4 x i32> @test_volatile_load_4xi32_align0(<4 x i32>* %loc) { 413 define <4 x i32> @test_volatile_load_4xi32_align0(<4 x i32>* %loc) {
414 ; CHECK-LABEL: test_volatile_load_4xi32_align0 414 ; CHECK-LABEL: test_volatile_load_4xi32_align0
415 ; CHECK-NEXT: %loaded = load volatile <4 x i32>* %loc, align 4 415 ; CHECK-NEXT: %loaded = load volatile <4 x i32>, <4 x i32>* %loc, align 4
416 ; CHECK-NEXT: ret <4 x i32> %loaded 416 ; CHECK-NEXT: ret <4 x i32> %loaded
417 %loaded = load volatile <4 x i32>* %loc 417 %loaded = load volatile <4 x i32>, <4 x i32>* %loc
418 ret <4 x i32> %loaded 418 ret <4 x i32> %loaded
419 } 419 }
420 420
421 define <4 x i32> @test_volatile_load_4xi32_align4(<4 x i32>* %loc) { 421 define <4 x i32> @test_volatile_load_4xi32_align4(<4 x i32>* %loc) {
422 ; CHECK-LABEL: test_volatile_load_4xi32_align4 422 ; CHECK-LABEL: test_volatile_load_4xi32_align4
423 ; CHECK-NEXT: %loaded = load volatile <4 x i32>* %loc, align 4 423 ; CHECK-NEXT: %loaded = load volatile <4 x i32>, <4 x i32>* %loc, align 4
424 ; CHECK-NEXT: ret <4 x i32> %loaded 424 ; CHECK-NEXT: ret <4 x i32> %loaded
425 %loaded = load volatile <4 x i32>* %loc, align 4 425 %loaded = load volatile <4 x i32>, <4 x i32>* %loc, align 4
426 ret <4 x i32> %loaded 426 ret <4 x i32> %loaded
427 } 427 }
428 428
429 define void @test_volatile_store_4xi32_align0(<4 x i32> %val, <4 x i32>* %loc) { 429 define void @test_volatile_store_4xi32_align0(<4 x i32> %val, <4 x i32>* %loc) {
430 ; CHECK-LABEL: test_volatile_store_4xi32_align0 430 ; CHECK-LABEL: test_volatile_store_4xi32_align0
431 ; CHECK-NEXT: store volatile <4 x i32> %val, <4 x i32>* %loc, align 4 431 ; CHECK-NEXT: store volatile <4 x i32> %val, <4 x i32>* %loc, align 4
432 ; CHECK-NEXT: ret void 432 ; CHECK-NEXT: ret void
433 store volatile <4 x i32> %val, <4 x i32>* %loc 433 store volatile <4 x i32> %val, <4 x i32>* %loc
434 ret void 434 ret void
435 } 435 }
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