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1 ; Test how we handle eliding ptrtoint instructions. | 1 ; Test how we handle eliding ptrtoint instructions. |
2 | 2 |
3 ; RUN: llvm-as < %s | pnacl-freeze \ | 3 ; RUN: llvm-as < %s | pnacl-freeze \ |
4 ; RUN: | pnacl-bcanalyzer -dump-records \ | 4 ; RUN: | pnacl-bcanalyzer -dump-records \ |
5 ; RUN: | FileCheck %s -check-prefix=PF2 | 5 ; RUN: | FileCheck %s -check-prefix=PF2 |
6 | 6 |
7 ; RUN: llvm-as < %s | pnacl-freeze -allow-local-symbol-tables \ | 7 ; RUN: llvm-as < %s | pnacl-freeze -allow-local-symbol-tables \ |
8 ; RUN: | pnacl-thaw -allow-local-symbol-tables \ | 8 ; RUN: | pnacl-thaw -allow-local-symbol-tables \ |
9 ; RUN: | llvm-dis - | FileCheck %s -check-prefix=TD2 | 9 ; RUN: | llvm-dis - | FileCheck %s -check-prefix=TD2 |
10 | 10 |
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533 ; Show that if a phi node refers to a pointer cast, we add | 533 ; Show that if a phi node refers to a pointer cast, we add |
534 ; them at the end of the incoming block. | 534 ; them at the end of the incoming block. |
535 define void @PhiBackwardRefs(i1) { | 535 define void @PhiBackwardRefs(i1) { |
536 %2 = alloca i8, i32 4, align 8 | 536 %2 = alloca i8, i32 4, align 8 |
537 %3 = bitcast i8* %2 to i32* | 537 %3 = bitcast i8* %2 to i32* |
538 %4 = alloca i8, i32 4, align 8 | 538 %4 = alloca i8, i32 4, align 8 |
539 %5 = ptrtoint i8* %4 to i32 | 539 %5 = ptrtoint i8* %4 to i32 |
540 br i1 %0, label %true, label %false | 540 br i1 %0, label %true, label %false |
541 | 541 |
542 true: | 542 true: |
543 %6 = load i32* %3 | 543 %6 = load i32, i32* %3 |
544 br label %merge | 544 br label %merge |
545 | 545 |
546 false: | 546 false: |
547 %7 = load i32* %3 | 547 %7 = load i32, i32* %3 |
548 br label %merge | 548 br label %merge |
549 | 549 |
550 merge: | 550 merge: |
551 %8 = phi i32 [%5, %true], [%5, %false] | 551 %8 = phi i32 [%5, %true], [%5, %false] |
552 %9 = phi i32 [%6, %true], [%7, %false] | 552 %9 = phi i32 [%6, %true], [%7, %false] |
553 ret void | 553 ret void |
554 } | 554 } |
555 | 555 |
556 ; TD2: define void @PhiBackwardRefs(i1) { | 556 ; TD2: define void @PhiBackwardRefs(i1) { |
557 ; TD2-NEXT: %2 = alloca i8, i32 4, align 8 | 557 ; TD2-NEXT: %2 = alloca i8, i32 4, align 8 |
558 ; TD2-NEXT: %3 = alloca i8, i32 4, align 8 | 558 ; TD2-NEXT: %3 = alloca i8, i32 4, align 8 |
559 ; TD2-NEXT: br i1 %0, label %true, label %false | 559 ; TD2-NEXT: br i1 %0, label %true, label %false |
560 ; TD2: true: | 560 ; TD2: true: |
561 ; TD2-NEXT: %4 = bitcast i8* %2 to i32* | 561 ; TD2-NEXT: %4 = bitcast i8* %2 to i32* |
562 ; TD2-NEXT: %5 = load i32* %4 | 562 ; TD2-NEXT: %5 = load i32, i32* %4 |
563 ; TD2-NEXT: %6 = ptrtoint i8* %3 to i32 | 563 ; TD2-NEXT: %6 = ptrtoint i8* %3 to i32 |
564 ; TD2-NEXT: br label %merge | 564 ; TD2-NEXT: br label %merge |
565 ; TD2: false: | 565 ; TD2: false: |
566 ; TD2-NEXT: %7 = bitcast i8* %2 to i32* | 566 ; TD2-NEXT: %7 = bitcast i8* %2 to i32* |
567 ; TD2-NEXT: %8 = load i32* %7 | 567 ; TD2-NEXT: %8 = load i32, i32* %7 |
568 ; TD2-NEXT: %9 = ptrtoint i8* %3 to i32 | 568 ; TD2-NEXT: %9 = ptrtoint i8* %3 to i32 |
569 ; TD2-NEXT: br label %merge | 569 ; TD2-NEXT: br label %merge |
570 ; TD2: merge: | 570 ; TD2: merge: |
571 ; TD2-NEXT: %10 = phi i32 [ %6, %true ], [ %9, %false ] | 571 ; TD2-NEXT: %10 = phi i32 [ %6, %true ], [ %9, %false ] |
572 ; TD2-NEXT: %11 = phi i32 [ %5, %true ], [ %8, %false ] | 572 ; TD2-NEXT: %11 = phi i32 [ %5, %true ], [ %8, %false ] |
573 ; TD2-NEXT: ret void | 573 ; TD2-NEXT: ret void |
574 ; TD2-NEXT: } | 574 ; TD2-NEXT: } |
575 | 575 |
576 ; PF2: <FUNCTION_BLOCK> | 576 ; PF2: <FUNCTION_BLOCK> |
577 ; PF2: </CONSTANTS_BLOCK> | 577 ; PF2: </CONSTANTS_BLOCK> |
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593 ; instructions instead of backwards references. | 593 ; instructions instead of backwards references. |
594 define void @PhiForwardRefs(i1) { | 594 define void @PhiForwardRefs(i1) { |
595 br label %start | 595 br label %start |
596 | 596 |
597 merge: | 597 merge: |
598 %2 = phi i32 [%9, %true], [%9, %false] | 598 %2 = phi i32 [%9, %true], [%9, %false] |
599 %3 = phi i32 [%4, %true], [%5, %false] | 599 %3 = phi i32 [%4, %true], [%5, %false] |
600 ret void | 600 ret void |
601 | 601 |
602 true: | 602 true: |
603 %4 = load i32* %7 | 603 %4 = load i32, i32* %7 |
604 br label %merge | 604 br label %merge |
605 | 605 |
606 false: | 606 false: |
607 %5 = load i32* %7 | 607 %5 = load i32, i32* %7 |
608 br label %merge | 608 br label %merge |
609 | 609 |
610 start: | 610 start: |
611 %6 = alloca i8, i32 4, align 8 | 611 %6 = alloca i8, i32 4, align 8 |
612 %7 = bitcast i8* %6 to i32* | 612 %7 = bitcast i8* %6 to i32* |
613 %8 = alloca i8, i32 4, align 8 | 613 %8 = alloca i8, i32 4, align 8 |
614 %9 = ptrtoint i8* %8 to i32 | 614 %9 = ptrtoint i8* %8 to i32 |
615 br i1 %0, label %true, label %false | 615 br i1 %0, label %true, label %false |
616 } | 616 } |
617 | 617 |
618 ; TD2: define void @PhiForwardRefs(i1) { | 618 ; TD2: define void @PhiForwardRefs(i1) { |
619 ; TD2-NEXT: br label %start | 619 ; TD2-NEXT: br label %start |
620 ; TD2: merge | 620 ; TD2: merge |
621 ; TD2-NEXT: %2 = phi i32 [ %11, %true ], [ %11, %false ] | 621 ; TD2-NEXT: %2 = phi i32 [ %11, %true ], [ %11, %false ] |
622 ; TD2-NEXT: %3 = phi i32 [ %5, %true ], [ %7, %false ] | 622 ; TD2-NEXT: %3 = phi i32 [ %5, %true ], [ %7, %false ] |
623 ; TD2-NEXT: ret void | 623 ; TD2-NEXT: ret void |
624 ; TD2: true: | 624 ; TD2: true: |
625 ; TD2-NEXT: %4 = inttoptr i32 %9 to i32* | 625 ; TD2-NEXT: %4 = inttoptr i32 %9 to i32* |
626 ; TD2-NEXT: %5 = load i32* %4 | 626 ; TD2-NEXT: %5 = load i32, i32* %4 |
627 ; TD2-NEXT: br label %merge | 627 ; TD2-NEXT: br label %merge |
628 ; TD2: false: | 628 ; TD2: false: |
629 ; TD2-NEXT: %6 = inttoptr i32 %9 to i32* | 629 ; TD2-NEXT: %6 = inttoptr i32 %9 to i32* |
630 ; TD2-NEXT: %7 = load i32* %6 | 630 ; TD2-NEXT: %7 = load i32, i32* %6 |
631 ; TD2-NEXT: br label %merge | 631 ; TD2-NEXT: br label %merge |
632 ; TD2: start: | 632 ; TD2: start: |
633 ; TD2-NEXT: %8 = alloca i8, i32 4, align 8 | 633 ; TD2-NEXT: %8 = alloca i8, i32 4, align 8 |
634 ; TD2-NEXT: %9 = ptrtoint i8* %8 to i32 | 634 ; TD2-NEXT: %9 = ptrtoint i8* %8 to i32 |
635 ; TD2-NEXT: %10 = alloca i8, i32 4, align 8 | 635 ; TD2-NEXT: %10 = alloca i8, i32 4, align 8 |
636 ; TD2-NEXT: %11 = ptrtoint i8* %10 to i32 | 636 ; TD2-NEXT: %11 = ptrtoint i8* %10 to i32 |
637 ; TD2-NEXT: br i1 %0, label %true, label %false | 637 ; TD2-NEXT: br i1 %0, label %true, label %false |
638 ; TD2-NEXT: } | 638 ; TD2-NEXT: } |
639 | 639 |
640 ; PF2: <FUNCTION_BLOCK> | 640 ; PF2: <FUNCTION_BLOCK> |
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662 ; we use it instead of adding one at the end of the block. In this | 662 ; we use it instead of adding one at the end of the block. In this |
663 ; example, we reuse instruction %7 in block true for phi node %10. | 663 ; example, we reuse instruction %7 in block true for phi node %10. |
664 define void @PhiMergeCast(i1) { | 664 define void @PhiMergeCast(i1) { |
665 %2 = alloca i8, i32 4, align 8 | 665 %2 = alloca i8, i32 4, align 8 |
666 %3 = bitcast i8* %2 to i32* | 666 %3 = bitcast i8* %2 to i32* |
667 %4 = alloca i8, i32 4, align 8 | 667 %4 = alloca i8, i32 4, align 8 |
668 %5 = ptrtoint i8* %4 to i32 | 668 %5 = ptrtoint i8* %4 to i32 |
669 br i1 %0, label %true, label %false | 669 br i1 %0, label %true, label %false |
670 | 670 |
671 true: | 671 true: |
672 %6 = load i32* %3 | 672 %6 = load i32, i32* %3 |
673 %7 = ptrtoint i8* %4 to i32 | 673 %7 = ptrtoint i8* %4 to i32 |
674 %8 = add i32 %6, %7 | 674 %8 = add i32 %6, %7 |
675 br label %merge | 675 br label %merge |
676 | 676 |
677 false: | 677 false: |
678 %9 = load i32* %3 | 678 %9 = load i32, i32* %3 |
679 br label %merge | 679 br label %merge |
680 | 680 |
681 merge: | 681 merge: |
682 %10 = phi i32 [%5, %true], [%5, %false] | 682 %10 = phi i32 [%5, %true], [%5, %false] |
683 %11 = phi i32 [%6, %true], [%9, %false] | 683 %11 = phi i32 [%6, %true], [%9, %false] |
684 ret void | 684 ret void |
685 } | 685 } |
686 | 686 |
687 ; TD2: define void @PhiMergeCast(i1) { | 687 ; TD2: define void @PhiMergeCast(i1) { |
688 ; TD2-NEXT: %2 = alloca i8, i32 4, align 8 | 688 ; TD2-NEXT: %2 = alloca i8, i32 4, align 8 |
689 ; TD2-NEXT: %3 = alloca i8, i32 4, align 8 | 689 ; TD2-NEXT: %3 = alloca i8, i32 4, align 8 |
690 ; TD2-NEXT: br i1 %0, label %true, label %false | 690 ; TD2-NEXT: br i1 %0, label %true, label %false |
691 ; TD2: true: | 691 ; TD2: true: |
692 ; TD2-NEXT: %4 = bitcast i8* %2 to i32* | 692 ; TD2-NEXT: %4 = bitcast i8* %2 to i32* |
693 ; TD2-NEXT: %5 = load i32* %4 | 693 ; TD2-NEXT: %5 = load i32, i32* %4 |
694 ; TD2-NEXT: %6 = ptrtoint i8* %3 to i32 | 694 ; TD2-NEXT: %6 = ptrtoint i8* %3 to i32 |
695 ; TD2-NEXT: %7 = add i32 %5, %6 | 695 ; TD2-NEXT: %7 = add i32 %5, %6 |
696 ; TD2-NEXT: br label %merge | 696 ; TD2-NEXT: br label %merge |
697 ; TD2: false: | 697 ; TD2: false: |
698 ; TD2-NEXT: %8 = bitcast i8* %2 to i32* | 698 ; TD2-NEXT: %8 = bitcast i8* %2 to i32* |
699 ; TD2-NEXT: %9 = load i32* %8 | 699 ; TD2-NEXT: %9 = load i32, i32* %8 |
700 ; TD2-NEXT: %10 = ptrtoint i8* %3 to i32 | 700 ; TD2-NEXT: %10 = ptrtoint i8* %3 to i32 |
701 ; TD2-NEXT: br label %merge | 701 ; TD2-NEXT: br label %merge |
702 ; TD2: merge: | 702 ; TD2: merge: |
703 ; TD2-NEXT: %11 = phi i32 [ %6, %true ], [ %10, %false ] | 703 ; TD2-NEXT: %11 = phi i32 [ %6, %true ], [ %10, %false ] |
704 ; TD2-NEXT: %12 = phi i32 [ %5, %true ], [ %9, %false ] | 704 ; TD2-NEXT: %12 = phi i32 [ %5, %true ], [ %9, %false ] |
705 ; TD2-NEXT: ret void | 705 ; TD2-NEXT: ret void |
706 ; TD2-NEXT: } | 706 ; TD2-NEXT: } |
707 | 707 |
708 ; PF2: <FUNCTION_BLOCK> | 708 ; PF2: <FUNCTION_BLOCK> |
709 ; PF2: </CONSTANTS_BLOCK> | 709 ; PF2: </CONSTANTS_BLOCK> |
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802 ; PF2-NEXT: <INST_STORE op0=4 op1=1 op2=1/> | 802 ; PF2-NEXT: <INST_STORE op0=4 op1=1 op2=1/> |
803 ; PF2-NEXT: <INST_STORE op0=4 op1=1 op2=1/> | 803 ; PF2-NEXT: <INST_STORE op0=4 op1=1 op2=1/> |
804 ; PF2-NEXT: <INST_RET/> | 804 ; PF2-NEXT: <INST_RET/> |
805 ; PF2-NEXT: <INST_STORE op0=4 op1=1 op2=1/> | 805 ; PF2-NEXT: <INST_STORE op0=4 op1=1 op2=1/> |
806 ; PF2-NEXT: <INST_STORE op0=4 op1=1 op2=1/> | 806 ; PF2-NEXT: <INST_STORE op0=4 op1=1 op2=1/> |
807 ; PF2-NEXT: <INST_RET/> | 807 ; PF2-NEXT: <INST_RET/> |
808 ; PF2-NEXT: <INST_STORE op0=4 op1=1 op2=1/> | 808 ; PF2-NEXT: <INST_STORE op0=4 op1=1 op2=1/> |
809 ; PF2-NEXT: <INST_STORE op0=4 op1=1 op2=1/> | 809 ; PF2-NEXT: <INST_STORE op0=4 op1=1 op2=1/> |
810 ; PF2-NEXT: <INST_RET/> | 810 ; PF2-NEXT: <INST_RET/> |
811 ; PF2: </FUNCTION_BLOCK> | 811 ; PF2: </FUNCTION_BLOCK> |
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