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1 ; RUN: pnacl-llc -mtriple=armv7a-none-nacl-gnueabi %s -filetype=obj \ | 1 ; RUN: pnacl-llc -mtriple=armv7a-none-nacl-gnueabi %s -filetype=obj \ |
2 ; RUN: -relocation-model=pic -mattr=+neon \ | 2 ; RUN: -relocation-model=pic -mattr=+neon \ |
3 ; RUN: -O0 -mcpu=cortex-a9 -o - \ | 3 ; RUN: -O0 -mcpu=cortex-a9 -o - \ |
4 ; RUN: | llvm-objdump -disassemble -r -triple armv7 - | FileCheck %s | 4 ; RUN: | llvm-objdump -disassemble -r -triple armv7 - | FileCheck %s |
5 | 5 |
6 ; This test exercises NaCl (which doesn't use constant islands) | 6 ; This test exercises NaCl (which doesn't use constant islands) |
7 ; together with -relocation-model=pic, to see that a movw/movt | 7 ; together with -relocation-model=pic, to see that a movw/movt |
8 ; is actually generated as expected. Use -O0 so that movw/movt | 8 ; is actually generated as expected. Use -O0 so that movw/movt |
9 ; are scheduled to be adjacent, instead of having other independent | 9 ; are scheduled to be adjacent, instead of having other independent |
10 ; instructions interleaved. | 10 ; instructions interleaved. |
11 | 11 |
12 %struct.object = type { [16 x i8*] } | 12 %struct.object = type { [16 x i8*] } |
13 | 13 |
14 @__do_eh_ctor.object = internal global %struct.object zeroinitializer, align 8 | 14 @__do_eh_ctor.object = internal global %struct.object zeroinitializer, align 8 |
15 @__EH_FRAME_BEGIN__ = internal global [0 x i8] zeroinitializer, section ".eh_fra
me", align 4 | 15 @__EH_FRAME_BEGIN__ = internal global [0 x i8] zeroinitializer, section ".eh_fra
me", align 4 |
16 @llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* }
{ i32 65535, void ()* @__do_eh_ctor }] | 16 @llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* }
{ i32 65535, void ()* @__do_eh_ctor }] |
17 | 17 |
18 declare void @__register_frame_info(i8* %begin, %struct.object* %ob) | 18 declare void @__register_frame_info(i8* %begin, %struct.object* %ob) |
19 | 19 |
20 define internal void @__do_eh_ctor() { | 20 define internal void @__do_eh_ctor() { |
21 entry: | 21 entry: |
22 call void @__register_frame_info(i8* getelementptr inbounds ([0 x i8]* @__EH_F
RAME_BEGIN__, i32 0, i32 0), %struct.object* @__do_eh_ctor.object) | 22 call void @__register_frame_info(i8* getelementptr inbounds ([0 x i8], [0 x i8
]* @__EH_FRAME_BEGIN__, i32 0, i32 0), %struct.object* @__do_eh_ctor.object) |
23 ; CHECK-LABEL: __do_eh_ctor | 23 ; CHECK-LABEL: __do_eh_ctor |
24 | 24 |
25 ; CHECK: movw r[[REG0:[0-9]+]] | 25 ; CHECK: movw r[[REG0:[0-9]+]] |
26 ; CHECK-NEXT: R_ARM_MOVW_PREL_NC .LCPI | 26 ; CHECK-NEXT: R_ARM_MOVW_PREL_NC .LCPI |
27 ; CHECK-NEXT: movt r[[REG0]] | 27 ; CHECK-NEXT: movt r[[REG0]] |
28 ; CHECK-NEXT: R_ARM_MOVT_PREL .LCPI | 28 ; CHECK-NEXT: R_ARM_MOVT_PREL .LCPI |
29 ; CHECK-NEXT: add r[[REG0]], pc, r[[REG0]] | 29 ; CHECK-NEXT: add r[[REG0]], pc, r[[REG0]] |
30 ; CHECK: ldr r[[REG0]], {{\[}}r[[REG0]]{{\]}} | 30 ; CHECK: ldr r[[REG0]], {{\[}}r[[REG0]]{{\]}} |
31 | 31 |
32 ; CHECK: movw r[[REG1:[0-9]+]] | 32 ; CHECK: movw r[[REG1:[0-9]+]] |
33 ; CHECK-NEXT: R_ARM_MOVW_PREL_NC _GLOBAL_OFFSET_TABLE_ | 33 ; CHECK-NEXT: R_ARM_MOVW_PREL_NC _GLOBAL_OFFSET_TABLE_ |
34 ; CHECK-NEXT: movt r[[REG1]] | 34 ; CHECK-NEXT: movt r[[REG1]] |
35 ; CHECK-NEXT: R_ARM_MOVT_PREL _GLOBAL_OFFSET_TABLE_ | 35 ; CHECK-NEXT: R_ARM_MOVT_PREL _GLOBAL_OFFSET_TABLE_ |
36 ; CHECK-NEXT: add r[[REG1]], pc, r[[REG1]] | 36 ; CHECK-NEXT: add r[[REG1]], pc, r[[REG1]] |
37 ; CHECK: add r[[REG0]], r[[REG0]], r[[REG1]] | 37 ; CHECK: add r[[REG0]], r[[REG0]], r[[REG1]] |
38 | 38 |
39 ; CHECK: movw r[[REG2:[0-9]+]] | 39 ; CHECK: movw r[[REG2:[0-9]+]] |
40 ; CHECK-NEXT: R_ARM_MOVW_PREL_NC .LCPI | 40 ; CHECK-NEXT: R_ARM_MOVW_PREL_NC .LCPI |
41 ; CHECK-NEXT: movt r[[REG2]] | 41 ; CHECK-NEXT: movt r[[REG2]] |
42 ; CHECK-NEXT: R_ARM_MOVT_PREL .LCPI | 42 ; CHECK-NEXT: R_ARM_MOVT_PREL .LCPI |
43 ; CHECK-NEXT: add r[[REG2]], pc, r[[REG2]] | 43 ; CHECK-NEXT: add r[[REG2]], pc, r[[REG2]] |
44 ; CHECK: ldr r[[REG2]], {{\[}}r[[REG2]]{{\]}} | 44 ; CHECK: ldr r[[REG2]], {{\[}}r[[REG2]]{{\]}} |
45 ; CHECK: add r[[REG1]], r[[REG2]], r[[REG1]] | 45 ; CHECK: add r[[REG1]], r[[REG2]], r[[REG1]] |
46 | 46 |
47 ret void | 47 ret void |
48 } | 48 } |
49 | 49 |
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