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1 ; RUN: llc -mtriple=armv7 < %s | FileCheck %s | 1 ; RUN: llc -mtriple=armv7 < %s | FileCheck %s |
2 ; RUN: llc -mtriple=armv7-unknown-nacl < %s | FileCheck %s -check-prefix=NACL | 2 ; RUN: llc -mtriple=armv7-unknown-nacl < %s | FileCheck %s -check-prefix=NACL |
3 | 3 |
4 ; Make sure NaCl doesn't generate register-register loads, which are disallowed | 4 ; Make sure NaCl doesn't generate register-register loads, which are disallowed |
5 ; by its sandbox. | 5 ; by its sandbox. |
6 | 6 |
7 @i16_large = internal global [516 x i8] undef | 7 @i16_large = internal global [516 x i8] undef |
8 | 8 |
9 define void @test() { | 9 define void @test() { |
10 %i = ptrtoint [516 x i8]* @i16_large to i32 | 10 %i = ptrtoint [516 x i8]* @i16_large to i32 |
11 %a = add i32 %i, 512 | 11 %a = add i32 %i, 512 |
12 %a.asptr = inttoptr i32 %a to i16* | 12 %a.asptr = inttoptr i32 %a to i16* |
13 %loaded = load atomic i16* %a.asptr seq_cst, align 2 | 13 %loaded = load atomic i16, i16* %a.asptr seq_cst, align 2 |
14 ret void | 14 ret void |
15 } | 15 } |
16 ; CHECK-LABEL: test: | 16 ; CHECK-LABEL: test: |
17 ; CHECK: ldrh r0, [r1, r0] | 17 ; CHECK: ldrh r0, [r1, r0] |
18 | 18 |
19 ; NACL-LABEL: test: | 19 ; NACL-LABEL: test: |
20 ; NACL: movw r0, :lower16:i16_large | 20 ; NACL: movw r0, :lower16:i16_large |
21 ; NACL: movt r0, :upper16:i16_large | 21 ; NACL: movt r0, :upper16:i16_large |
22 ; NACL: add r0, r0, #512 | 22 ; NACL: add r0, r0, #512 |
23 ; NACL: ldrh r0, [r0] | 23 ; NACL: ldrh r0, [r0] |
24 ; NACL: dmb ish | 24 ; NACL: dmb ish |
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