Changes from 3.7 merge to files not in upstream

lib/Target/X86/X86NaClRewritePass.cpp

 //=== X86NaClRewritePAss.cpp - Rewrite instructions for NaCl SFI --*- C++ -*-=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains a pass that ensures stores and loads and stack/frame
@@ skipping 242 matching lines @@
     MI.getOperand(1).setReg(X86::RBP);
     MI.setDesc(TII->get(X86::MOV64rr));
     Opc = X86::MOV64rr;
   }
 
   // "MOV RBP, RSP" is already safe
   if (Opc == X86::MOV64rr && MI.getOperand(1).getReg() == X86::RBP) {
     return true;
   }
 
-  //  Promote 32-bit lea to 64-bit lea (does this ever happen?)
   assert(Opc != X86::LEA32r && "Invalid opcode in 64-bit mode!");
-  if (Opc == X86::LEA64_32r) {
-    unsigned DestReg = MI.getOperand(0).getReg();
+  if (Opc == X86::LEA64_32r){
     unsigned BaseReg = MI.getOperand(1).getReg();
-    unsigned Scale   = MI.getOperand(2).getImm();
-    unsigned IndexReg = MI.getOperand(3).getReg();
-    assert(DestReg == X86::ESP);
-    assert(Scale == 1);
-    assert(BaseReg == X86::EBP);
-    assert(IndexReg == 0);
-    MI.getOperand(0).setReg(X86::RSP);
-    MI.getOperand(1).setReg(X86::RBP);
-    MI.setDesc(TII->get(X86::LEA64r));
-    Opc = X86::LEA64r;
+    if (BaseReg == X86::EBP) {
+      // leal N(%ebp), %esp can be promoted to leaq N(%rbp), %rsp, which
+      // converts to SPAJDi32 below.
+      unsigned DestReg = MI.getOperand(0).getReg();
+      unsigned Scale   = MI.getOperand(2).getImm();
+      unsigned IndexReg = MI.getOperand(3).getReg();
+      assert(DestReg == X86::ESP);
+      assert(Scale == 1);
+      assert(BaseReg == X86::EBP);
+      assert(IndexReg == 0);
+      MI.getOperand(0).setReg(X86::RSP);
+      MI.getOperand(1).setReg(X86::RBP);
+      MI.setDesc(TII->get(X86::LEA64r));
+      Opc = X86::LEA64r;
+    } else {
+      // Create a MachineInstr bundle (i.e. a bundle-locked group) and fix up
+      // the stack pointer by adding R15.  TODO(dschuff): generalize this for
+      // other uses if needed, and try to replace some pseudos if
+      // possible. Eventually replace with auto-sandboxing.
+      auto NextMBBI = MBBI;
+      ++NextMBBI;
+      BuildMI(MBB, NextMBBI, MBBI->getDebugLoc(),
+              TII->get(X86::ADD64rr), X86::RSP)
+          .addReg(X86::RSP).addReg(X86::R15);
+      MIBundleBuilder(MBB, MBBI, NextMBBI);
+      finalizeBundle(MBB, MBBI.getInstrIterator());
+      return true;
+    }
   }
 
   if (Opc == X86::LEA64r && MatchesSPAdj(MI)) {
     const MachineOperand &Offset = MI.getOperand(4);
     BuildMI(MBB, MBBI, DL, TII->get(X86::NACL_SPADJi32))
       .addImm(Offset.getImm())
       .addReg(FlagUseZeroBasedSandbox ? 0 : X86::R15);
     MI.eraseFromParent();
     return true;
   }
@@ skipping 410 matching lines @@
   }
   return Modified;
 }
 
 bool X86NaClRewritePass::runOnMachineFunction(MachineFunction &MF) {
   bool Modified = false;
 
   TM = &MF.getTarget();
   TII = MF.getSubtarget().getInstrInfo();
   TRI = MF.getSubtarget().getRegisterInfo();
-  Subtarget = &TM->getSubtarget<X86Subtarget>();
+  Subtarget = &MF.getSubtarget<X86Subtarget>();
   Is64Bit = Subtarget->is64Bit();
 
   assert(Subtarget->isTargetNaCl() && "Unexpected target in NaClRewritePass!");
 
   DEBUG(dbgs() << "*************** NaCl Rewrite Pass ***************\n");
   for (MachineFunction::iterator MFI = MF.begin(), E = MF.end();
        MFI != E;
        ++MFI) {
     Modified |= runOnMachineBasicBlock(*MFI);
   }
@@ skipping 24 matching lines @@
   }
   return Modified;
 }
 
 /// createX86NaClRewritePassPass - returns an instance of the pass.
 namespace llvm {
   FunctionPass* createX86NaClRewritePass() {
     return new X86NaClRewritePass();
   }
 }