Changes from 3.7 merge to files not in upstream

lib/Target/ARM/MCTargetDesc/ARMMCNaCl.cpp

 //=== ARMMCNaCl.cpp -  Expansion of NaCl pseudo-instructions     --*- C++ -*-=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 //===----------------------------------------------------------------------===//
 #define DEBUG_TYPE "arm-mc-nacl"
 
+#include "ARMAddressingModes.h"
 #include "MCTargetDesc/ARMBaseInfo.h"
 #include "MCTargetDesc/ARMMCExpr.h"
 #include "MCTargetDesc/ARMMCNaCl.h"
 #include "MCTargetDesc/ARMMCTargetDesc.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 /// Two helper functions for emitting the actual guard instructions
 
 static void EmitBICMask(const MCSubtargetInfo &STI, MCStreamer &Out,
                         unsigned Addr, int64_t Pred, unsigned Mask) {
   // bic\Pred \Addr, \Addr, #Mask
   MCInst BICInst;
+  const int32_t EncodedMask = ARM_AM::getSOImmVal(Mask);
+  assert(EncodedMask != -1);
   BICInst.setOpcode(ARM::BICri);
   BICInst.addOperand(MCOperand::CreateReg(Addr)); // rD
   BICInst.addOperand(MCOperand::CreateReg(Addr)); // rS
-  BICInst.addOperand(MCOperand::CreateImm(Mask)); // imm
+  BICInst.addOperand(MCOperand::CreateImm(EncodedMask)); // imm
   BICInst.addOperand(MCOperand::CreateImm(Pred));  // predicate
   BICInst.addOperand(MCOperand::CreateReg(ARM::CPSR)); // CPSR
   BICInst.addOperand(MCOperand::CreateReg(0)); // flag out
   Out.EmitInstruction(BICInst, STI);
 }
 
 static void EmitTST(const MCSubtargetInfo &STI, MCStreamer &Out, unsigned Reg) {
   // tst \reg, #\MASK typically 0xc0000000
-  const unsigned Mask = 0xC0000000;
+  const int32_t Mask = ARM_AM::getSOImmVal(0xC0000000U);
+  assert(Mask != -1);
   MCInst TSTInst;
   TSTInst.setOpcode(ARM::TSTri);
   TSTInst.addOperand(MCOperand::CreateReg(Reg));  // rS
   TSTInst.addOperand(MCOperand::CreateImm(Mask)); // imm
   TSTInst.addOperand(MCOperand::CreateImm((int64_t)ARMCC::AL)); // Always
   TSTInst.addOperand(MCOperand::CreateImm(0)); // flag out
   Out.EmitInstruction(TSTInst, STI);
 }
 
 
@@ skipping 257 matching lines @@
   assert(State.RecursiveCall && "Illegal Depth");
   State.RecursiveCall = false;
 
   // We're done expanding a SFI guard. Reset state vars.
   State.SaveCount = 0;
   State.I = 0;
   return true;
 }
 
 } // namespace llvm