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Side by Side Diff: src/ia32/assembler-ia32.h

Issue 11498006: Revert 13157, 13145 and 13140: Crankshaft code stubs. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 8 years ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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58 // 58 //
59 // 3) By not using an enum, we are possibly preventing the compiler from 59 // 3) By not using an enum, we are possibly preventing the compiler from
60 // doing certain constant folds, which may significantly reduce the 60 // doing certain constant folds, which may significantly reduce the
61 // code generated for some assembly instructions (because they boil down 61 // code generated for some assembly instructions (because they boil down
62 // to a few constants). If this is a problem, we could change the code 62 // to a few constants). If this is a problem, we could change the code
63 // such that we use an enum in optimized mode, and the struct in debug 63 // such that we use an enum in optimized mode, and the struct in debug
64 // mode. This way we get the compile-time error checking in debug mode 64 // mode. This way we get the compile-time error checking in debug mode
65 // and best performance in optimized code. 65 // and best performance in optimized code.
66 // 66 //
67 struct Register { 67 struct Register {
68 static const int kMaxNumAllocatableRegisters = 6; 68 static const int kNumAllocatableRegisters = 6;
69 static int NumAllocatableRegisters() {
70 return kMaxNumAllocatableRegisters;
71 }
72 static const int kNumRegisters = 8; 69 static const int kNumRegisters = 8;
73 70
74 static inline const char* AllocationIndexToString(int index); 71 static inline const char* AllocationIndexToString(int index);
75 72
76 static inline int ToAllocationIndex(Register reg); 73 static inline int ToAllocationIndex(Register reg);
77 74
78 static inline Register FromAllocationIndex(int index); 75 static inline Register FromAllocationIndex(int index);
79 76
80 static Register from_code(int code) { 77 static Register from_code(int code) {
81 ASSERT(code >= 0); 78 ASSERT(code >= 0);
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
115 const Register edx = { kRegister_edx_Code }; 112 const Register edx = { kRegister_edx_Code };
116 const Register ebx = { kRegister_ebx_Code }; 113 const Register ebx = { kRegister_ebx_Code };
117 const Register esp = { kRegister_esp_Code }; 114 const Register esp = { kRegister_esp_Code };
118 const Register ebp = { kRegister_ebp_Code }; 115 const Register ebp = { kRegister_ebp_Code };
119 const Register esi = { kRegister_esi_Code }; 116 const Register esi = { kRegister_esi_Code };
120 const Register edi = { kRegister_edi_Code }; 117 const Register edi = { kRegister_edi_Code };
121 const Register no_reg = { kRegister_no_reg_Code }; 118 const Register no_reg = { kRegister_no_reg_Code };
122 119
123 120
124 inline const char* Register::AllocationIndexToString(int index) { 121 inline const char* Register::AllocationIndexToString(int index) {
125 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 122 ASSERT(index >= 0 && index < kNumAllocatableRegisters);
126 // This is the mapping of allocation indices to registers. 123 // This is the mapping of allocation indices to registers.
127 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" }; 124 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" };
128 return kNames[index]; 125 return kNames[index];
129 } 126 }
130 127
131 128
132 inline int Register::ToAllocationIndex(Register reg) { 129 inline int Register::ToAllocationIndex(Register reg) {
133 ASSERT(reg.is_valid() && !reg.is(esp) && !reg.is(ebp)); 130 ASSERT(reg.is_valid() && !reg.is(esp) && !reg.is(ebp));
134 return (reg.code() >= 6) ? reg.code() - 2 : reg.code(); 131 return (reg.code() >= 6) ? reg.code() - 2 : reg.code();
135 } 132 }
136 133
137 134
138 inline Register Register::FromAllocationIndex(int index) { 135 inline Register Register::FromAllocationIndex(int index) {
139 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 136 ASSERT(index >= 0 && index < kNumAllocatableRegisters);
140 return (index >= 4) ? from_code(index + 2) : from_code(index); 137 return (index >= 4) ? from_code(index + 2) : from_code(index);
141 } 138 }
142 139
143 140
144 struct IntelDoubleRegister { 141 struct XMMRegister {
145 static const int kMaxNumAllocatableRegisters = 7; 142 static const int kNumAllocatableRegisters = 7;
146 static int NumAllocatableRegisters(); 143 static const int kNumRegisters = 8;
147 static int NumRegisters();
148 static const char* AllocationIndexToString(int index);
149 144
150 static int ToAllocationIndex(IntelDoubleRegister reg) { 145 static int ToAllocationIndex(XMMRegister reg) {
151 ASSERT(reg.code() != 0); 146 ASSERT(reg.code() != 0);
152 return reg.code() - 1; 147 return reg.code() - 1;
153 } 148 }
154 149
155 static IntelDoubleRegister FromAllocationIndex(int index) { 150 static XMMRegister FromAllocationIndex(int index) {
156 ASSERT(index >= 0 && index < NumAllocatableRegisters()); 151 ASSERT(index >= 0 && index < kNumAllocatableRegisters);
157 return from_code(index + 1); 152 return from_code(index + 1);
158 } 153 }
159 154
160 static IntelDoubleRegister from_code(int code) {
161 IntelDoubleRegister result = { code };
162 return result;
163 }
164
165 bool is_valid() const {
166 return 0 <= code_ && code_ < NumRegisters();
167 }
168 int code() const {
169 ASSERT(is_valid());
170 return code_;
171 }
172
173 int code_;
174 };
175
176
177 const IntelDoubleRegister double_register_0 = { 0 };
178 const IntelDoubleRegister double_register_1 = { 1 };
179 const IntelDoubleRegister double_register_2 = { 2 };
180 const IntelDoubleRegister double_register_3 = { 3 };
181 const IntelDoubleRegister double_register_4 = { 4 };
182 const IntelDoubleRegister double_register_5 = { 5 };
183 const IntelDoubleRegister double_register_6 = { 6 };
184 const IntelDoubleRegister double_register_7 = { 7 };
185
186
187 struct XMMRegister : IntelDoubleRegister {
188 static const int kNumAllocatableRegisters = 7;
189 static const int kNumRegisters = 8;
190
191 static XMMRegister from_code(int code) {
192 STATIC_ASSERT(sizeof(XMMRegister) == sizeof(IntelDoubleRegister));
193 XMMRegister result;
194 result.code_ = code;
195 return result;
196 }
197
198 bool is(XMMRegister reg) const { return code_ == reg.code_; }
199
200 static XMMRegister FromAllocationIndex(int index) {
201 ASSERT(index >= 0 && index < NumAllocatableRegisters());
202 return from_code(index + 1);
203 }
204
205 static const char* AllocationIndexToString(int index) { 155 static const char* AllocationIndexToString(int index) {
206 ASSERT(index >= 0 && index < kNumAllocatableRegisters); 156 ASSERT(index >= 0 && index < kNumAllocatableRegisters);
207 const char* const names[] = { 157 const char* const names[] = {
208 "xmm1", 158 "xmm1",
209 "xmm2", 159 "xmm2",
210 "xmm3", 160 "xmm3",
211 "xmm4", 161 "xmm4",
212 "xmm5", 162 "xmm5",
213 "xmm6", 163 "xmm6",
214 "xmm7" 164 "xmm7"
215 }; 165 };
216 return names[index]; 166 return names[index];
217 } 167 }
218 };
219
220
221 #define xmm0 (static_cast<const XMMRegister&>(double_register_0))
222 #define xmm1 (static_cast<const XMMRegister&>(double_register_1))
223 #define xmm2 (static_cast<const XMMRegister&>(double_register_2))
224 #define xmm3 (static_cast<const XMMRegister&>(double_register_3))
225 #define xmm4 (static_cast<const XMMRegister&>(double_register_4))
226 #define xmm5 (static_cast<const XMMRegister&>(double_register_5))
227 #define xmm6 (static_cast<const XMMRegister&>(double_register_6))
228 #define xmm7 (static_cast<const XMMRegister&>(double_register_7))
229
230
231 struct X87TopOfStackRegister : IntelDoubleRegister {
232 static const int kNumAllocatableRegisters = 1;
233 static const int kNumRegisters = 1;
234
235 bool is(X87TopOfStackRegister reg) const {
236 return code_ == reg.code_;
237 }
238
239 static const char* AllocationIndexToString(int index) {
240 ASSERT(index >= 0 && index < kNumAllocatableRegisters);
241 const char* const names[] = {
242 "st0",
243 };
244 return names[index];
245 }
246 168
247 static int ToAllocationIndex(X87TopOfStackRegister reg) { 169 static XMMRegister from_code(int code) {
248 ASSERT(reg.code() == 0); 170 XMMRegister r = { code };
249 return 0; 171 return r;
250 } 172 }
173
174 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
175 bool is(XMMRegister reg) const { return code_ == reg.code_; }
176 int code() const {
177 ASSERT(is_valid());
178 return code_;
179 }
180
181 int code_;
251 }; 182 };
252 183
253 #define x87tos \ 184
254 static_cast<const X87TopOfStackRegister&>(double_register_0) 185 const XMMRegister xmm0 = { 0 };
186 const XMMRegister xmm1 = { 1 };
187 const XMMRegister xmm2 = { 2 };
188 const XMMRegister xmm3 = { 3 };
189 const XMMRegister xmm4 = { 4 };
190 const XMMRegister xmm5 = { 5 };
191 const XMMRegister xmm6 = { 6 };
192 const XMMRegister xmm7 = { 7 };
255 193
256 194
257 typedef IntelDoubleRegister DoubleRegister; 195 typedef XMMRegister DoubleRegister;
258 196
259 197
260 enum Condition { 198 enum Condition {
261 // any value < 0 is considered no_condition 199 // any value < 0 is considered no_condition
262 no_condition = -1, 200 no_condition = -1,
263 201
264 overflow = 0, 202 overflow = 0,
265 no_overflow = 1, 203 no_overflow = 1,
266 below = 2, 204 below = 2,
267 above_equal = 3, 205 above_equal = 3,
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1269 private: 1207 private:
1270 Assembler* assembler_; 1208 Assembler* assembler_;
1271 #ifdef DEBUG 1209 #ifdef DEBUG
1272 int space_before_; 1210 int space_before_;
1273 #endif 1211 #endif
1274 }; 1212 };
1275 1213
1276 } } // namespace v8::internal 1214 } } // namespace v8::internal
1277 1215
1278 #endif // V8_IA32_ASSEMBLER_IA32_H_ 1216 #endif // V8_IA32_ASSEMBLER_IA32_H_
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