MIPS: Add float instructions and test coverage, part two

src/mips64/disasm-mips64.cc

Index: src/mips64/disasm-mips64.cc
diff --git a/src/mips64/disasm-mips64.cc b/src/mips64/disasm-mips64.cc
index 7fcdb909d2ce498ccb22c6ac64bd03c6182120aa..67715ff2274dd5b759bca2597b17f587ca34654e 100644
--- a/src/mips64/disasm-mips64.cc
+++ b/src/mips64/disasm-mips64.cc
@@ -614,6 +614,9 @@ bool Decoder::DecodeTypeRegisterRsType(Instruction* instr) {
     case CEIL_L_D:
       Format(instr, "ceil.l.'t 'fd, 'fs");
       break;
+    case CLASS_D:
+      Format(instr, "class.'t 'fd, 'fs");
+      break;
     case CVT_S_D:
       Format(instr, "cvt.s.'t 'fd, 'fs");
       break;
@@ -677,6 +680,9 @@ void Decoder::DecodeTypeRegisterLRsType(Instruction* instr) {
     case CVT_S_L:
       Format(instr, "cvt.s.l 'fd, 'fs");
       break;
+    case CMP_AF:
+      Format(instr, "cmp.af.d  'fd,  'fs, 'ft");
+      break;
     case CMP_UN:
       Format(instr, "cmp.un.d  'fd,  'fs, 'ft");
       break;
@@ -1129,6 +1135,20 @@ void Decoder::DecodeTypeRegisterSPECIAL3(Instruction* instr) {
       Format(instr, "dext    'rt, 'rs, 'sa, 'ss1");
       break;
     }
+    case BITSWAP: {
+      Format(instr, "bitswap 'rd, 'rt");
+      break;
+    }
+    case DBITSWAP: {
+      switch (instr->SaFieldRaw()) {
+        case DBITSWAP_SA:
+          Format(instr, "dbitswap 'rd, 'rt");
+          break;
+        default:
+          UNREACHABLE();
+      }
+      break;
+    }
     default:
       UNREACHABLE();
   }