Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(531)

Side by Side Diff: test/cctest/test-disasm-mips64.cc

Issue 1145223002: MIPS: Add float instructions and test coverage, part two (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Addressed comments Created 5 years, 7 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « test/cctest/test-disasm-mips.cc ('k') | no next file » | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 651 matching lines...) Expand 10 before | Expand all | Expand 10 after
662 "7ef6ff84 ins s6, s7, 30, 2"); 662 "7ef6ff84 ins s6, s7, 30, 2");
663 COMPARE(ins_(v0, v1, 0, 32), 663 COMPARE(ins_(v0, v1, 0, 32),
664 "7c62f804 ins v0, v1, 0, 32"); 664 "7c62f804 ins v0, v1, 0, 32");
665 COMPARE(ext_(a0, a1, 31, 1), 665 COMPARE(ext_(a0, a1, 31, 1),
666 "7ca407c0 ext a0, a1, 31, 1"); 666 "7ca407c0 ext a0, a1, 31, 1");
667 COMPARE(ext_(s6, s7, 30, 2), 667 COMPARE(ext_(s6, s7, 30, 2),
668 "7ef60f80 ext s6, s7, 30, 2"); 668 "7ef60f80 ext s6, s7, 30, 2");
669 COMPARE(ext_(v0, v1, 0, 32), 669 COMPARE(ext_(v0, v1, 0, 32),
670 "7c62f800 ext v0, v1, 0, 32"); 670 "7c62f800 ext v0, v1, 0, 32");
671 671
672 COMPARE(add_s(f4, f6, f8), "46083100 add.s f4, f6, f8");
673 COMPARE(add_d(f12, f14, f16), "46307300 add.d f12, f14, f16");
674
675 if (kArchVariant == kMips64r6) {
676 COMPARE(bitswap(a0, a1), "7c052020 bitswap a0, a1");
677 COMPARE(bitswap(t8, s0), "7c10c020 bitswap t8, s0");
678 COMPARE(dbitswap(a0, a1), "7c052024 dbitswap a0, a1");
679 COMPARE(dbitswap(t8, s0), "7c10c024 dbitswap t8, s0");
680 }
681
682 COMPARE(abs_s(f6, f8), "46004185 abs.s f6, f8");
683 COMPARE(abs_d(f10, f12), "46206285 abs.d f10, f12");
684
685 COMPARE(div_s(f2, f4, f6), "46062083 div.s f2, f4, f6");
686 COMPARE(div_d(f2, f4, f6), "46262083 div.d f2, f4, f6");
687
672 VERIFY_RUN(); 688 VERIFY_RUN();
673 } 689 }
674 690
675 691
676 TEST(Type1) { 692 TEST(Type1) {
677 SET_UP(); 693 SET_UP();
678 if (kArchVariant == kMips64r6) { 694 if (kArchVariant == kMips64r6) {
679 COMPARE(seleqz(a0, a1, a2), "00a62035 seleqz a0, a1, a2"); 695 COMPARE(seleqz(a0, a1, a2), "00a62035 seleqz a0, a1, a2");
680 COMPARE(selnez(a0, a1, a2), "00a62037 selnez a0, a1, a2"); 696 COMPARE(selnez(a0, a1, a2), "00a62037 selnez a0, a1, a2");
681 697
(...skipping 74 matching lines...) Expand 10 before | Expand all | Expand 10 after
756 COMPARE(movt_d(f6, f4, 4), "46312191 movt.d f6, f4, cc(1)"); 772 COMPARE(movt_d(f6, f4, 4), "46312191 movt.d f6, f4, cc(1)");
757 773
758 COMPARE(movf_s(f6, f4, 4), "46102191 movf.s f6, f4, cc(1)"); 774 COMPARE(movf_s(f6, f4, 4), "46102191 movf.s f6, f4, cc(1)");
759 COMPARE(movf_d(f6, f4, 4), "46302191 movf.d f6, f4, cc(1)"); 775 COMPARE(movf_d(f6, f4, 4), "46302191 movf.d f6, f4, cc(1)");
760 776
761 COMPARE(movn_s(f6, f4, t0), "460c2193 movn.s f6, f4, t0"); 777 COMPARE(movn_s(f6, f4, t0), "460c2193 movn.s f6, f4, t0");
762 COMPARE(movn_d(f6, f4, t0), "462c2193 movn.d f6, f4, t0"); 778 COMPARE(movn_d(f6, f4, t0), "462c2193 movn.d f6, f4, t0");
763 } 779 }
764 VERIFY_RUN(); 780 VERIFY_RUN();
765 } 781 }
782
783
784 TEST(Type2) {
785 if (kArchVariant == kMips64r6) {
786 SET_UP();
787
788 COMPARE(class_s(f3, f4), "460020db class.s f3, f4");
789 COMPARE(class_d(f2, f3), "4620189b class.d f2, f3");
790
791 VERIFY_RUN();
792 }
793 }
794
795
796 TEST(C_FMT_DISASM) {
797 if (kArchVariant == kMips64r2) {
798 SET_UP();
799
800 COMPARE(c_s(F, f8, f10, 0), "460a4030 c.f.s f8, f10, cc(0)");
801 COMPARE(c_d(F, f8, f10, 0), "462a4030 c.f.d f8, f10, cc(0)");
802
803 COMPARE(c_s(UN, f8, f10, 2), "460a4231 c.un.s f8, f10, cc(2)");
804 COMPARE(c_d(UN, f8, f10, 2), "462a4231 c.un.d f8, f10, cc(2)");
805
806 COMPARE(c_s(EQ, f8, f10, 4), "460a4432 c.eq.s f8, f10, cc(4)");
807 COMPARE(c_d(EQ, f8, f10, 4), "462a4432 c.eq.d f8, f10, cc(4)");
808
809 COMPARE(c_s(UEQ, f8, f10, 6), "460a4633 c.ueq.s f8, f10, cc(6)");
810 COMPARE(c_d(UEQ, f8, f10, 6), "462a4633 c.ueq.d f8, f10, cc(6)");
811
812 COMPARE(c_s(OLT, f8, f10, 0), "460a4034 c.olt.s f8, f10, cc(0)");
813 COMPARE(c_d(OLT, f8, f10, 0), "462a4034 c.olt.d f8, f10, cc(0)");
814
815 COMPARE(c_s(ULT, f8, f10, 2), "460a4235 c.ult.s f8, f10, cc(2)");
816 COMPARE(c_d(ULT, f8, f10, 2), "462a4235 c.ult.d f8, f10, cc(2)");
817
818 COMPARE(c_s(OLE, f8, f10, 4), "460a4436 c.ole.s f8, f10, cc(4)");
819 COMPARE(c_d(OLE, f8, f10, 4), "462a4436 c.ole.d f8, f10, cc(4)");
820
821 COMPARE(c_s(ULE, f8, f10, 6), "460a4637 c.ule.s f8, f10, cc(6)");
822 COMPARE(c_d(ULE, f8, f10, 6), "462a4637 c.ule.d f8, f10, cc(6)");
823
824 VERIFY_RUN();
825 }
826 }
827
828
829 TEST(COND_FMT_DISASM) {
830 if (kArchVariant == kMips64r6) {
831 SET_UP();
832
833 COMPARE(cmp_s(F, f6, f8, f10), "468a4180 cmp.af.s f6, f8, f10");
834 COMPARE(cmp_d(F, f6, f8, f10), "46aa4180 cmp.af.d f6, f8, f10");
835
836 COMPARE(cmp_s(UN, f6, f8, f10), "468a4181 cmp.un.s f6, f8, f10");
837 COMPARE(cmp_d(UN, f6, f8, f10), "46aa4181 cmp.un.d f6, f8, f10");
838
839 COMPARE(cmp_s(EQ, f6, f8, f10), "468a4182 cmp.eq.s f6, f8, f10");
840 COMPARE(cmp_d(EQ, f6, f8, f10), "46aa4182 cmp.eq.d f6, f8, f10");
841
842 COMPARE(cmp_s(UEQ, f6, f8, f10), "468a4183 cmp.ueq.s f6, f8, f10");
843 COMPARE(cmp_d(UEQ, f6, f8, f10), "46aa4183 cmp.ueq.d f6, f8, f10");
844
845 COMPARE(cmp_s(LT, f6, f8, f10), "468a4184 cmp.lt.s f6, f8, f10");
846 COMPARE(cmp_d(LT, f6, f8, f10), "46aa4184 cmp.lt.d f6, f8, f10");
847
848 COMPARE(cmp_s(ULT, f6, f8, f10), "468a4185 cmp.ult.s f6, f8, f10");
849 COMPARE(cmp_d(ULT, f6, f8, f10), "46aa4185 cmp.ult.d f6, f8, f10");
850
851 COMPARE(cmp_s(LE, f6, f8, f10), "468a4186 cmp.le.s f6, f8, f10");
852 COMPARE(cmp_d(LE, f6, f8, f10), "46aa4186 cmp.le.d f6, f8, f10");
853
854 COMPARE(cmp_s(ULE, f6, f8, f10), "468a4187 cmp.ule.s f6, f8, f10");
855 COMPARE(cmp_d(ULE, f6, f8, f10), "46aa4187 cmp.ule.d f6, f8, f10");
856
857 COMPARE(cmp_s(ORD, f6, f8, f10), "468a4191 cmp.or.s f6, f8, f10");
858 COMPARE(cmp_d(ORD, f6, f8, f10), "46aa4191 cmp.or.d f6, f8, f10");
859
860 COMPARE(cmp_s(UNE, f6, f8, f10), "468a4192 cmp.une.s f6, f8, f10");
861 COMPARE(cmp_d(UNE, f6, f8, f10), "46aa4192 cmp.une.d f6, f8, f10");
862
863 COMPARE(cmp_s(NE, f6, f8, f10), "468a4193 cmp.ne.s f6, f8, f10");
864 COMPARE(cmp_d(NE, f6, f8, f10), "46aa4193 cmp.ne.d f6, f8, f10");
865
866 VERIFY_RUN();
867 }
868 }
869
870
871 TEST(CVT_DISSASM) {
872 SET_UP();
873 COMPARE(cvt_d_s(f22, f24), "4600c5a1 cvt.d.s f22, f24");
874 COMPARE(cvt_d_w(f22, f24), "4680c5a1 cvt.d.w f22, f24");
875 if (kArchVariant == kMips64r6 || kArchVariant == kMips64r2) {
876 COMPARE(cvt_d_l(f22, f24), "46a0c5a1 cvt.d.l f22, f24");
877 }
878
879 if (kArchVariant == kMips64r6 || kArchVariant == kMips64r2) {
880 COMPARE(cvt_l_s(f22, f24), "4600c5a5 cvt.l.s f22, f24");
881 COMPARE(cvt_l_d(f22, f24), "4620c5a5 cvt.l.d f22, f24");
882 }
883
884 COMPARE(cvt_s_d(f22, f24), "4620c5a0 cvt.s.d f22, f24");
885 COMPARE(cvt_s_w(f22, f24), "4680c5a0 cvt.s.w f22, f24");
886 if (kArchVariant == kMips64r6 || kArchVariant == kMips64r2) {
887 COMPARE(cvt_s_l(f22, f24), "46a0c5a0 cvt.s.l f22, f24");
888 }
889
890 COMPARE(cvt_s_d(f22, f24), "4620c5a0 cvt.s.d f22, f24");
891 COMPARE(cvt_s_w(f22, f24), "4680c5a0 cvt.s.w f22, f24");
892
893 VERIFY_RUN();
894 }
OLDNEW
« no previous file with comments | « test/cctest/test-disasm-mips.cc ('k') | no next file » | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698