MIPS: Add float instructions and test coverage, part two

src/mips64/disasm-mips64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 596 matching lines @@
       break;
     case FLOOR_L_D:
       Format(instr, "floor.l.'t 'fd, 'fs");
       break;
     case CEIL_W_D:
       Format(instr, "ceil.w.'t 'fd, 'fs");
       break;
     case CEIL_L_D:
       Format(instr, "ceil.l.'t 'fd, 'fs");
       break;
+    case CLASS_D:
+      Format(instr, "class.'t 'fd, 'fs");
+      break;
     case CVT_S_D:
       Format(instr, "cvt.s.'t 'fd, 'fs");
       break;
     case C_F_D:
       Format(instr, "c.f.'t   'fs, 'ft, 'Cc");
       break;
     case C_UN_D:
       Format(instr, "c.un.'t  'fs, 'ft, 'Cc");
       break;
     case C_EQ_D:
@@ skipping 43 matching lines @@
 
 
 void Decoder::DecodeTypeRegisterLRsType(Instruction* instr) {
   switch (instr->FunctionFieldRaw()) {
     case CVT_D_L:
       Format(instr, "cvt.d.l 'fd, 'fs");
       break;
     case CVT_S_L:
       Format(instr, "cvt.s.l 'fd, 'fs");
       break;
+    case CMP_AF:
+      Format(instr, "cmp.af.d  'fd,  'fs, 'ft");
+      break;
     case CMP_UN:
       Format(instr, "cmp.un.d  'fd,  'fs, 'ft");
       break;
     case CMP_EQ:
       Format(instr, "cmp.eq.d  'fd,  'fs, 'ft");
       break;
     case CMP_UEQ:
       Format(instr, "cmp.ueq.d  'fd,  'fs, 'ft");
       break;
     case CMP_LT:
@@ skipping 432 matching lines @@
       break;
     }
     case EXT: {
       Format(instr, "ext     'rt, 'rs, 'sa, 'ss1");
       break;
     }
     case DEXT: {
       Format(instr, "dext    'rt, 'rs, 'sa, 'ss1");
       break;
     }
+    case BITSWAP: {
+      Format(instr, "bitswap 'rd, 'rt");
+      break;
+    }
+    case DBITSWAP: {
+      switch (instr->SaFieldRaw()) {
+        case DBITSWAP_SA:
+          Format(instr, "dbitswap 'rd, 'rt");
+          break;
+        default:
+          UNREACHABLE();
+      }
+      break;
+    }
     default:
       UNREACHABLE();
   }
 }
 
 
 int Decoder::DecodeTypeRegister(Instruction* instr) {
   switch (instr->OpcodeFieldRaw()) {
     case COP1:  // Coprocessor instructions.
       DecodeTypeRegisterCOP1(instr);
@@ skipping 421 matching lines @@
         prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 #undef UNSUPPORTED
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_MIPS64