MIPS: Add float instructions and test coverage, part two

src/mips64/constants-mips64.h

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef  V8_MIPS_CONSTANTS_H_
 #define  V8_MIPS_CONSTANTS_H_
 
 // UNIMPLEMENTED_ macro for MIPS.
 #ifdef DEBUG
 #define UNIMPLEMENTED_MIPS()                                                  \
@@ skipping 425 matching lines @@
   // SPECIAL3 Encoding of Function Field.
   EXT = ((0 << 3) + 0),
   DEXTM = ((0 << 3) + 1),
   DEXTU = ((0 << 3) + 2),
   DEXT = ((0 << 3) + 3),
   INS = ((0 << 3) + 4),
   DINSM = ((0 << 3) + 5),
   DINSU = ((0 << 3) + 6),
   DINS = ((0 << 3) + 7),
 
+  BITSWAP = ((4 << 3) + 0),
+  DBITSWAP = ((4 << 3) + 4),
   DSBH = ((4 << 3) + 4),
 
+  // SPECIAL3 Encoding of sa Field.
+  DBITSWAP_SA = ((0 << 3) + 0) << kSaShift,
+
   // REGIMM  encoding of rt Field.
   BLTZ = ((0 << 3) + 0) << 16,
   BGEZ = ((0 << 3) + 1) << 16,
   BLTZAL = ((2 << 3) + 0) << 16,
   BGEZAL = ((2 << 3) + 1) << 16,
   BGEZALL = ((2 << 3) + 3) << 16,
   DAHI = ((0 << 3) + 6) << 16,
   DATI = ((3 << 3) + 6) << 16,
 
   // COP1 Encoding of rs Field.
   MFC1 = ((0 << 3) + 0) << 21,
   DMFC1 = ((0 << 3) + 1) << 21,
   CFC1 = ((0 << 3) + 2) << 21,
   MFHC1 = ((0 << 3) + 3) << 21,
   MTC1 = ((0 << 3) + 4) << 21,
   DMTC1 = ((0 << 3) + 5) << 21,
   CTC1 = ((0 << 3) + 6) << 21,
   MTHC1 = ((0 << 3) + 7) << 21,
   BC1 = ((1 << 3) + 0) << 21,
   S = ((2 << 3) + 0) << 21,
   D = ((2 << 3) + 1) << 21,
   W = ((2 << 3) + 4) << 21,
   L = ((2 << 3) + 5) << 21,
   PS = ((2 << 3) + 6) << 21,
   // COP1 Encoding of Function Field When rs=S.
+
   ADD_S = ((0 << 3) + 0),
   SUB_S = ((0 << 3) + 1),
   MUL_S = ((0 << 3) + 2),
   DIV_S = ((0 << 3) + 3),
   ABS_S = ((0 << 3) + 5),
   SQRT_S = ((0 << 3) + 4),
   MOV_S = ((0 << 3) + 6),
   NEG_S = ((0 << 3) + 7),
   ROUND_L_S = ((1 << 3) + 0),
   TRUNC_L_S = ((1 << 3) + 1),
   CEIL_L_S = ((1 << 3) + 2),
   FLOOR_L_S = ((1 << 3) + 3),
   ROUND_W_S = ((1 << 3) + 4),
   TRUNC_W_S = ((1 << 3) + 5),
   CEIL_W_S = ((1 << 3) + 6),
   FLOOR_W_S = ((1 << 3) + 7),
   RECIP_S = ((2 << 3) + 5),
   RSQRT_S = ((2 << 3) + 6),
+  CLASS_S = ((3 << 3) + 3),
   CVT_D_S = ((4 << 3) + 1),
   CVT_W_S = ((4 << 3) + 4),
   CVT_L_S = ((4 << 3) + 5),
   CVT_PS_S = ((4 << 3) + 6),
   // COP1 Encoding of Function Field When rs=D.
   ADD_D = ((0 << 3) + 0),
   SUB_D = ((0 << 3) + 1),
   MUL_D = ((0 << 3) + 2),
   DIV_D = ((0 << 3) + 3),
   SQRT_D = ((0 << 3) + 4),
   ABS_D = ((0 << 3) + 5),
   MOV_D = ((0 << 3) + 6),
   NEG_D = ((0 << 3) + 7),
   ROUND_L_D = ((1 << 3) + 0),
   TRUNC_L_D = ((1 << 3) + 1),
   CEIL_L_D = ((1 << 3) + 2),
   FLOOR_L_D = ((1 << 3) + 3),
   ROUND_W_D = ((1 << 3) + 4),
   TRUNC_W_D = ((1 << 3) + 5),
   CEIL_W_D = ((1 << 3) + 6),
   FLOOR_W_D = ((1 << 3) + 7),
   RECIP_D = ((2 << 3) + 5),
   RSQRT_D = ((2 << 3) + 6),
+  CLASS_D = ((3 << 3) + 3),
+  MIN = ((3 << 3) + 4),
+  MINA = ((3 << 3) + 5),
+  MAX = ((3 << 3) + 6),
+  MAXA = ((3 << 3) + 7),
   CVT_S_D = ((4 << 3) + 0),
   CVT_W_D = ((4 << 3) + 4),
   CVT_L_D = ((4 << 3) + 5),
   C_F_D = ((6 << 3) + 0),
   C_UN_D = ((6 << 3) + 1),
   C_EQ_D = ((6 << 3) + 2),
   C_UEQ_D = ((6 << 3) + 3),
   C_OLT_D = ((6 << 3) + 4),
   C_ULT_D = ((6 << 3) + 5),
   C_OLE_D = ((6 << 3) + 6),
   C_ULE_D = ((6 << 3) + 7),
+
   // COP1 Encoding of Function Field When rs=W or L.
   CVT_S_W = ((4 << 3) + 0),
   CVT_D_W = ((4 << 3) + 1),
   CVT_S_L = ((4 << 3) + 0),
   CVT_D_L = ((4 << 3) + 1),
   BC1EQZ = ((2 << 2) + 1) << 21,
   BC1NEZ = ((3 << 2) + 1) << 21,
   // COP1 CMP positive predicates Bit 5..4 = 00.
   CMP_AF = ((0 << 3) + 0),
   CMP_UN = ((0 << 3) + 1),
@@ skipping 22 matching lines @@
   CMP_OGT = ((2 << 3) + 7),  // Reserved, not implemented.
   CMP_SAT = ((3 << 3) + 0),  // Reserved, not implemented.
   CMP_SOR = ((3 << 3) + 1),
   CMP_SUNE = ((3 << 3) + 2),
   CMP_SNE = ((3 << 3) + 3),
   CMP_SUGE = ((3 << 3) + 4),  // Reserved, not implemented.
   CMP_SOGE = ((3 << 3) + 5),  // Reserved, not implemented.
   CMP_SUGT = ((3 << 3) + 6),  // Reserved, not implemented.
   CMP_SOGT = ((3 << 3) + 7),  // Reserved, not implemented.
 
-  MIN = ((3 << 3) + 4),
-  MINA = ((3 << 3) + 5),
-  MAX = ((3 << 3) + 6),
-  MAXA = ((3 << 3) + 7),
   SEL = ((2 << 3) + 0),
   MOVF = ((2 << 3) + 1),      // Function field for MOVT.fmt and MOVF.fmt
   MOVZ_C = ((2 << 3) + 2),    // COP1 on FPR registers.
   MOVN_C = ((2 << 3) + 3),    // COP1 on FPR registers.
   SELEQZ_C = ((2 << 3) + 4),  // COP1 on FPR registers.
   SELNEZ_C = ((2 << 3) + 7),  // COP1 on FPR registers.
 
   // COP1 Encoding of Function Field When rs=PS.
   // COP1X Encoding of Function Field.
   MADD_D = ((4 << 3) + 1),
@@ skipping 124 matching lines @@
     default:
       return cc;
   }
 }
 
 
 // ----- Coprocessor conditions.
 enum FPUCondition {
   kNoFPUCondition = -1,
 
-  F     = 0,  // False.
-  UN    = 1,  // Unordered.
-  EQ    = 2,  // Equal.
-  UEQ   = 3,  // Unordered or Equal.
-  OLT   = 4,  // Ordered or Less Than.
-  ULT   = 5,  // Unordered or Less Than.
-  OLE   = 6,  // Ordered or Less Than or Equal.
-  ULE   = 7   // Unordered or Less Than or Equal.
+  F = 0x00,    // False.
+  UN = 0x01,   // Unordered.
+  EQ = 0x02,   // Equal.
+  UEQ = 0x03,  // Unordered or Equal.
+  OLT = 0x04,  // Ordered or Less Than, on Mips release < 6.
+  LT = 0x04,   // Ordered or Less Than, on Mips release >= 6.
+  ULT = 0x05,  // Unordered or Less Than.
+  OLE = 0x06,  // Ordered or Less Than or Equal, on Mips release < 6.
+  LE = 0x06,   // Ordered or Less Than or Equal, on Mips release >= 6.
+  ULE = 0x07,  // Unordered or Less Than or Equal.
+
+  // Following constants are available on Mips release >= 6 only.
+  ORD = 0x11,  // Ordered, on Mips release >= 6.
+  UNE = 0x12,  // Not equal, on Mips release >= 6.
+  NE = 0x13,   // Ordered Greater Than or Less Than. on Mips >= 6 only.
 };
 
 
 // FPU rounding modes.
 enum FPURoundingMode {
   RN = 0 << 0,  // Round to Nearest.
   RZ = 1 << 0,  // Round towards zero.
   RP = 2 << 0,  // Round towards Plus Infinity.
   RM = 3 << 0,  // Round towards Minus Infinity.
 
@@ skipping 261 matching lines @@
 // TODO(plind): below should be based on kPointerSize
 // TODO(plind): find all usages and remove the needless instructions for n64.
 const int kCArgsSlotsSize = kCArgSlotCount * Instruction::kInstrSize * 2;
 
 const int kInvalidStackOffset = -1;
 const int kBranchReturnOffset = 2 * Instruction::kInstrSize;
 
 } }   // namespace v8::internal
 
 #endif    // #ifndef V8_MIPS_CONSTANTS_H_