MIPS: Add float instructions and test coverage, part two

src/mips64/assembler-mips64.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 889 matching lines @@
   void movt_d(FPURegister fd, FPURegister fs, uint16_t cc);
   void movf_s(FPURegister fd, FPURegister fs, uint16_t cc);
   void movf_d(FPURegister fd, FPURegister fs, uint16_t cc);
   void movn_s(FPURegister fd, FPURegister fs, Register rt);
   void movn_d(FPURegister fd, FPURegister fs, Register rt);
   // Bit twiddling.
   void clz(Register rd, Register rs);
   void ins_(Register rt, Register rs, uint16_t pos, uint16_t size);
   void ext_(Register rt, Register rs, uint16_t pos, uint16_t size);
   void dext_(Register rt, Register rs, uint16_t pos, uint16_t size);
+  void bitswap(Register rd, Register rt);
+  void dbitswap(Register rd, Register rt);
 
   // --------Coprocessor-instructions----------------
 
   // Load, store, and move.
   void lwc1(FPURegister fd, const MemOperand& src);
   void ldc1(FPURegister fd, const MemOperand& src);
 
   void swc1(FPURegister fs, const MemOperand& dst);
   void sdc1(FPURegister fs, const MemOperand& dst);
 
@@ skipping 51 matching lines @@
   void cvt_l_d(FPURegister fd, FPURegister fs);
   void trunc_l_s(FPURegister fd, FPURegister fs);
   void trunc_l_d(FPURegister fd, FPURegister fs);
   void round_l_s(FPURegister fd, FPURegister fs);
   void round_l_d(FPURegister fd, FPURegister fs);
   void floor_l_s(FPURegister fd, FPURegister fs);
   void floor_l_d(FPURegister fd, FPURegister fs);
   void ceil_l_s(FPURegister fd, FPURegister fs);
   void ceil_l_d(FPURegister fd, FPURegister fs);
 
+  void class_s(FPURegister fd, FPURegister fs);
+  void class_d(FPURegister fd, FPURegister fs);
+
   void min(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft);
   void mina(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft);
   void max(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft);
   void maxa(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft);
   void min_s(FPURegister fd, FPURegister fs, FPURegister ft);
   void min_d(FPURegister fd, FPURegister fs, FPURegister ft);
   void max_s(FPURegister fd, FPURegister fs, FPURegister ft);
   void max_d(FPURegister fd, FPURegister fs, FPURegister ft);
   void mina_s(FPURegister fd, FPURegister fs, FPURegister ft);
   void mina_d(FPURegister fd, FPURegister fs, FPURegister ft);
   void maxa_s(FPURegister fd, FPURegister fs, FPURegister ft);
   void maxa_d(FPURegister fd, FPURegister fs, FPURegister ft);
 
   void cvt_s_w(FPURegister fd, FPURegister fs);
   void cvt_s_l(FPURegister fd, FPURegister fs);
   void cvt_s_d(FPURegister fd, FPURegister fs);
 
   void cvt_d_w(FPURegister fd, FPURegister fs);
   void cvt_d_l(FPURegister fd, FPURegister fs);
   void cvt_d_s(FPURegister fd, FPURegister fs);
 
   // Conditions and branches for MIPSr6.
   void cmp(FPUCondition cond, SecondaryField fmt,
          FPURegister fd, FPURegister ft, FPURegister fs);
+  void cmp_s(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft);
+  void cmp_d(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft);
 
   void bc1eqz(int16_t offset, FPURegister ft);
   void bc1eqz(Label* L, FPURegister ft) {
     bc1eqz(branch_offset(L, false)>>2, ft);
   }
   void bc1nez(int16_t offset, FPURegister ft);
   void bc1nez(Label* L, FPURegister ft) {
     bc1nez(branch_offset(L, false)>>2, ft);
   }
 
   // Conditions and branches for non MIPSr6.
   void c(FPUCondition cond, SecondaryField fmt,
          FPURegister ft, FPURegister fs, uint16_t cc = 0);
+  void c_s(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0);
+  void c_d(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0);
 
   void bc1f(int16_t offset, uint16_t cc = 0);
   void bc1f(Label* L, uint16_t cc = 0) {
     bc1f(branch_offset(L, false)>>2, cc);
   }
   void bc1t(int16_t offset, uint16_t cc = 0);
   void bc1t(Label* L, uint16_t cc = 0) {
     bc1t(branch_offset(L, false)>>2, cc);
   }
   void fcmp(FPURegister src1, const double src2, FPUCondition cond);
@@ skipping 441 matching lines @@
 class EnsureSpace BASE_EMBEDDED {
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBuffer();
   }
 };
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM_ASSEMBLER_MIPS_H_