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Issue 1145063003: Do not emit debug check in optimized IC stubs (Closed) Base URL: https://github.com/dart-lang/sdk.git@master
Patch Set: a Created 5 years, 6 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" 5 #include "vm/globals.h"
6 #if defined(TARGET_ARCH_MIPS) 6 #if defined(TARGET_ARCH_MIPS)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/code_generator.h" 9 #include "vm/code_generator.h"
10 #include "vm/compiler.h" 10 #include "vm/compiler.h"
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1436 // - If receiver is Smi -> load Smi class. 1436 // - If receiver is Smi -> load Smi class.
1437 // - If receiver is not-Smi -> load receiver's class. 1437 // - If receiver is not-Smi -> load receiver's class.
1438 // - Check if 'num_args' (including receiver) match any IC data group. 1438 // - Check if 'num_args' (including receiver) match any IC data group.
1439 // - Match found -> jump to target. 1439 // - Match found -> jump to target.
1440 // - Match not found -> jump to IC miss. 1440 // - Match not found -> jump to IC miss.
1441 void StubCode::GenerateNArgsCheckInlineCacheStub( 1441 void StubCode::GenerateNArgsCheckInlineCacheStub(
1442 Assembler* assembler, 1442 Assembler* assembler,
1443 intptr_t num_args, 1443 intptr_t num_args,
1444 const RuntimeEntry& handle_ic_miss, 1444 const RuntimeEntry& handle_ic_miss,
1445 Token::Kind kind, 1445 Token::Kind kind,
1446 RangeCollectionMode range_collection_mode) { 1446 RangeCollectionMode range_collection_mode,
1447 bool optimized) {
1447 __ Comment("NArgsCheckInlineCacheStub"); 1448 __ Comment("NArgsCheckInlineCacheStub");
1448 ASSERT(num_args > 0); 1449 ASSERT(num_args > 0);
1449 #if defined(DEBUG) 1450 #if defined(DEBUG)
1450 { Label ok; 1451 { Label ok;
1451 // Check that the IC data array has NumArgsTested() == num_args. 1452 // Check that the IC data array has NumArgsTested() == num_args.
1452 // 'NumArgsTested' is stored in the least significant bits of 'state_bits'. 1453 // 'NumArgsTested' is stored in the least significant bits of 'state_bits'.
1453 __ lw(T0, FieldAddress(S5, ICData::state_bits_offset())); 1454 __ lw(T0, FieldAddress(S5, ICData::state_bits_offset()));
1454 ASSERT(ICData::NumArgsTestedShift() == 0); // No shift needed. 1455 ASSERT(ICData::NumArgsTestedShift() == 0); // No shift needed.
1455 __ andi(T0, T0, Immediate(ICData::NumArgsTestedMask())); 1456 __ andi(T0, T0, Immediate(ICData::NumArgsTestedMask()));
1456 __ BranchEqual(T0, Immediate(num_args), &ok); 1457 __ BranchEqual(T0, Immediate(num_args), &ok);
1457 __ Stop("Incorrect stub for IC data"); 1458 __ Stop("Incorrect stub for IC data");
1458 __ Bind(&ok); 1459 __ Bind(&ok);
1459 } 1460 }
1460 #endif // DEBUG 1461 #endif // DEBUG
1461 1462
1462 1463
1463 Label stepping, done_stepping; 1464 Label stepping, done_stepping;
1464 if (FLAG_support_debugger) { 1465 if (FLAG_support_debugger && !optimized) {
1465 __ Comment("Check single stepping"); 1466 __ Comment("Check single stepping");
1466 __ LoadIsolate(T0); 1467 __ LoadIsolate(T0);
1467 __ lbu(T0, Address(T0, Isolate::single_step_offset())); 1468 __ lbu(T0, Address(T0, Isolate::single_step_offset()));
1468 __ BranchNotEqual(T0, Immediate(0), &stepping); 1469 __ BranchNotEqual(T0, Immediate(0), &stepping);
1469 __ Bind(&done_stepping); 1470 __ Bind(&done_stepping);
1470 } 1471 }
1471 1472
1472 __ Comment("Range feedback collection"); 1473 __ Comment("Range feedback collection");
1473 Label not_smi_or_overflow; 1474 Label not_smi_or_overflow;
1474 if (range_collection_mode == kCollectRanges) { 1475 if (range_collection_mode == kCollectRanges) {
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1644 __ UpdateRangeFeedback(V0, 2, S5, T1, &done); 1645 __ UpdateRangeFeedback(V0, 2, S5, T1, &done);
1645 __ Bind(&done); 1646 __ Bind(&done);
1646 __ addiu(SP, SP, Immediate(frame_size * kWordSize)); 1647 __ addiu(SP, SP, Immediate(frame_size * kWordSize));
1647 __ LeaveStubFrame(); 1648 __ LeaveStubFrame();
1648 __ Ret(); 1649 __ Ret();
1649 } else { 1650 } else {
1650 __ jr(T4); 1651 __ jr(T4);
1651 } 1652 }
1652 1653
1653 // Call single step callback in debugger. 1654 // Call single step callback in debugger.
1654 if (FLAG_support_debugger) { 1655 if (FLAG_support_debugger && !optimized) {
1655 __ Bind(&stepping); 1656 __ Bind(&stepping);
1656 __ EnterStubFrame(); 1657 __ EnterStubFrame();
1657 __ addiu(SP, SP, Immediate(-2 * kWordSize)); 1658 __ addiu(SP, SP, Immediate(-2 * kWordSize));
1658 __ sw(S5, Address(SP, 1 * kWordSize)); // Preserve IC data. 1659 __ sw(S5, Address(SP, 1 * kWordSize)); // Preserve IC data.
1659 __ sw(RA, Address(SP, 0 * kWordSize)); // Return address. 1660 __ sw(RA, Address(SP, 0 * kWordSize)); // Return address.
1660 __ CallRuntime(kSingleStepHandlerRuntimeEntry, 0); 1661 __ CallRuntime(kSingleStepHandlerRuntimeEntry, 0);
1661 __ lw(RA, Address(SP, 0 * kWordSize)); 1662 __ lw(RA, Address(SP, 0 * kWordSize));
1662 __ lw(S5, Address(SP, 1 * kWordSize)); 1663 __ lw(S5, Address(SP, 1 * kWordSize));
1663 __ addiu(SP, SP, Immediate(2 * kWordSize)); 1664 __ addiu(SP, SP, Immediate(2 * kWordSize));
1664 __ LeaveStubFrame(); 1665 __ LeaveStubFrame();
(...skipping 70 matching lines...) Expand 10 before | Expand all | Expand 10 after
1735 Token::kILLEGAL, 1736 Token::kILLEGAL,
1736 kCollectRanges); 1737 kCollectRanges);
1737 } 1738 }
1738 1739
1739 1740
1740 void StubCode::GenerateOneArgOptimizedCheckInlineCacheStub( 1741 void StubCode::GenerateOneArgOptimizedCheckInlineCacheStub(
1741 Assembler* assembler) { 1742 Assembler* assembler) {
1742 GenerateOptimizedUsageCounterIncrement(assembler); 1743 GenerateOptimizedUsageCounterIncrement(assembler);
1743 GenerateNArgsCheckInlineCacheStub(assembler, 1, 1744 GenerateNArgsCheckInlineCacheStub(assembler, 1,
1744 kInlineCacheMissHandlerOneArgRuntimeEntry, Token::kILLEGAL, 1745 kInlineCacheMissHandlerOneArgRuntimeEntry, Token::kILLEGAL,
1745 kIgnoreRanges); 1746 kIgnoreRanges, true /* optimized */);
1746 } 1747 }
1747 1748
1748 1749
1749 void StubCode::GenerateTwoArgsOptimizedCheckInlineCacheStub( 1750 void StubCode::GenerateTwoArgsOptimizedCheckInlineCacheStub(
1750 Assembler* assembler) { 1751 Assembler* assembler) {
1751 GenerateOptimizedUsageCounterIncrement(assembler); 1752 GenerateOptimizedUsageCounterIncrement(assembler);
1752 GenerateNArgsCheckInlineCacheStub(assembler, 2, 1753 GenerateNArgsCheckInlineCacheStub(assembler, 2,
1753 kInlineCacheMissHandlerTwoArgsRuntimeEntry, Token::kILLEGAL, 1754 kInlineCacheMissHandlerTwoArgsRuntimeEntry, Token::kILLEGAL,
1754 kIgnoreRanges); 1755 kIgnoreRanges, true /* optimized */);
1755 } 1756 }
1756 1757
1757 1758
1758 // Intermediary stub between a static call and its target. ICData contains 1759 // Intermediary stub between a static call and its target. ICData contains
1759 // the target function and the call count. 1760 // the target function and the call count.
1760 // S5: ICData 1761 // S5: ICData
1761 void StubCode::GenerateZeroArgsUnoptimizedStaticCallStub(Assembler* assembler) { 1762 void StubCode::GenerateZeroArgsUnoptimizedStaticCallStub(Assembler* assembler) {
1762 GenerateUsageCounterIncrement(assembler, T0); 1763 GenerateUsageCounterIncrement(assembler, T0);
1763 __ Comment("UnoptimizedStaticCallStub"); 1764 __ Comment("UnoptimizedStaticCallStub");
1764 #if defined(DEBUG) 1765 #if defined(DEBUG)
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2294 // Result: 2295 // Result:
2295 // T1: entry point. 2296 // T1: entry point.
2296 void StubCode::GenerateMegamorphicLookupStub(Assembler* assembler) { 2297 void StubCode::GenerateMegamorphicLookupStub(Assembler* assembler) {
2297 EmitMegamorphicLookup(assembler, T0, T1, T1); 2298 EmitMegamorphicLookup(assembler, T0, T1, T1);
2298 __ Ret(); 2299 __ Ret();
2299 } 2300 }
2300 2301
2301 } // namespace dart 2302 } // namespace dart
2302 2303
2303 #endif // defined TARGET_ARCH_MIPS 2304 #endif // defined TARGET_ARCH_MIPS
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