Use ldr for movs out of stack slots (instead of mov reg, [sp/fp]).

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstARM32 and OperandARM32 classes,
@@ skipping 295 matching lines @@
   Inst::dump(Func);
 }
 
 template <> void InstARM32Mov::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Variable *Dest = getDest();
   if (Dest->hasReg()) {
-    Str << "\t"
-        << "mov" << getPredicate() << "\t";
+    const char *Opcode = "mov";
+    Operand *Src0 = getSrc(0);
+    if (const auto *Src0V = llvm::dyn_cast<Variable>(Src0)) {
+      if (!Src0V->hasReg()) {
+        Opcode = "ldr"; // Always load the full stack slot (vs ldrb, ldrh).
+      }
+    } else {
+      // If Src isn't a variable, it shouldn't be a memory operand either
+      // (otherwise Opcode will have to be ldr).
+      assert(!llvm::isa<OperandARM32Mem>(Src0));
+    }
+    Str << "\t" << Opcode << getPredicate() << "\t";
     getDest()->emit(Func);
     Str << ", ";
     getSrc(0)->emit(Func);
   } else {
     Variable *Src0 = llvm::cast<Variable>(getSrc(0));
     assert(Src0->hasReg());
     Str << "\t"
         << "str" << getPredicate() << "\t";
     Src0->emit(Func);
     Str << ", ";
@@ skipping 387 matching lines @@
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     if (Func)
       getShiftAmt()->dump(Func);
     else
       getShiftAmt()->dump(Str);
   }
 }
 
 } // end of namespace Ice