| Index: src/mips/constants-mips.h
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| diff --git a/src/mips/constants-mips.h b/src/mips/constants-mips.h
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| index bdeb8c060b2c0e6f97a41490506d860f5d12f28c..37ac2336bfd184542e5ad5712bdaa5541878921e 100644
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| --- a/src/mips/constants-mips.h
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| +++ b/src/mips/constants-mips.h
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| @@ -259,9 +259,15 @@ const int kSaBits        = 5;
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|  const int kFunctionShift = 0;
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|  const int kFunctionBits  = 6;
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|  const int kLuiShift      = 16;
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| +const int kBp2Shift = 6;
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| +const int kBp2Bits = 2;
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|  
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|  const int kImm16Shift = 0;
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|  const int kImm16Bits  = 16;
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| +const int kImm18Shift = 0;
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| +const int kImm18Bits = 18;
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| +const int kImm19Shift = 0;
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| +const int kImm19Bits = 19;
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|  const int kImm21Shift = 0;
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|  const int kImm21Bits  = 21;
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|  const int kImm26Shift = 0;
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| @@ -294,6 +300,9 @@ const int kFBtrueBits    = 1;
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|  // Instruction bit masks.
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|  const int  kOpcodeMask   = ((1 << kOpcodeBits) - 1) << kOpcodeShift;
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|  const int  kImm16Mask    = ((1 << kImm16Bits) - 1) << kImm16Shift;
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| +const int kImm18Mask = ((1 << kImm18Bits) - 1) << kImm18Shift;
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| +const int kImm19Mask = ((1 << kImm19Bits) - 1) << kImm19Shift;
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| +const int kImm21Mask = ((1 << kImm21Bits) - 1) << kImm21Shift;
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|  const int  kImm26Mask    = ((1 << kImm26Bits) - 1) << kImm26Shift;
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|  const int  kImm28Mask    = ((1 << kImm28Bits) - 1) << kImm28Shift;
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|  const int  kRsFieldMask  = ((1 << kRsBits) - 1) << kRsShift;
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| @@ -311,60 +320,63 @@ const int  kJumpAddrMask = (1 << (kImm26Bits + kImmFieldShift)) - 1;
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|  // We use this presentation to stay close to the table representation in
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|  // MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set.
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|  enum Opcode {
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| -  SPECIAL   =   0 << kOpcodeShift,
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| -  REGIMM    =   1 << kOpcodeShift,
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| -
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| -  J         =   ((0 << 3) + 2) << kOpcodeShift,
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| -  JAL       =   ((0 << 3) + 3) << kOpcodeShift,
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| -  BEQ       =   ((0 << 3) + 4) << kOpcodeShift,
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| -  BNE       =   ((0 << 3) + 5) << kOpcodeShift,
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| -  BLEZ      =   ((0 << 3) + 6) << kOpcodeShift,
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| -  BGTZ      =   ((0 << 3) + 7) << kOpcodeShift,
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| -
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| -  ADDI      =   ((1 << 3) + 0) << kOpcodeShift,
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| -  ADDIU     =   ((1 << 3) + 1) << kOpcodeShift,
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| -  SLTI      =   ((1 << 3) + 2) << kOpcodeShift,
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| -  SLTIU     =   ((1 << 3) + 3) << kOpcodeShift,
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| -  ANDI      =   ((1 << 3) + 4) << kOpcodeShift,
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| -  ORI       =   ((1 << 3) + 5) << kOpcodeShift,
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| -  XORI      =   ((1 << 3) + 6) << kOpcodeShift,
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| -  LUI       =   ((1 << 3) + 7) << kOpcodeShift,  // LUI/AUI family.
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| -
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| -  BEQC      =   ((2 << 3) + 0) << kOpcodeShift,
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| -  COP1      =   ((2 << 3) + 1) << kOpcodeShift,  // Coprocessor 1 class.
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| -  BEQL      =   ((2 << 3) + 4) << kOpcodeShift,
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| -  BNEL      =   ((2 << 3) + 5) << kOpcodeShift,
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| -  BLEZL     =   ((2 << 3) + 6) << kOpcodeShift,
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| -  BGTZL     =   ((2 << 3) + 7) << kOpcodeShift,
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| -
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| -  DADDI     =   ((3 << 3) + 0) << kOpcodeShift,  // This is also BNEC.
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| -  SPECIAL2  =   ((3 << 3) + 4) << kOpcodeShift,
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| -  SPECIAL3  =   ((3 << 3) + 7) << kOpcodeShift,
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| -
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| -  LB        =   ((4 << 3) + 0) << kOpcodeShift,
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| -  LH        =   ((4 << 3) + 1) << kOpcodeShift,
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| -  LWL       =   ((4 << 3) + 2) << kOpcodeShift,
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| -  LW        =   ((4 << 3) + 3) << kOpcodeShift,
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| -  LBU       =   ((4 << 3) + 4) << kOpcodeShift,
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| -  LHU       =   ((4 << 3) + 5) << kOpcodeShift,
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| -  LWR       =   ((4 << 3) + 6) << kOpcodeShift,
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| -  SB        =   ((5 << 3) + 0) << kOpcodeShift,
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| -  SH        =   ((5 << 3) + 1) << kOpcodeShift,
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| -  SWL       =   ((5 << 3) + 2) << kOpcodeShift,
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| -  SW        =   ((5 << 3) + 3) << kOpcodeShift,
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| -  SWR       =   ((5 << 3) + 6) << kOpcodeShift,
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| -
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| -  LWC1      =   ((6 << 3) + 1) << kOpcodeShift,
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| -  LDC1      =   ((6 << 3) + 5) << kOpcodeShift,
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| -  BEQZC     =   ((6 << 3) + 6) << kOpcodeShift,
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| -
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| -  PREF      =   ((6 << 3) + 3) << kOpcodeShift,
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| -
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| -  SWC1      =   ((7 << 3) + 1) << kOpcodeShift,
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| -  SDC1      =   ((7 << 3) + 5) << kOpcodeShift,
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| -  BNEZC     =   ((7 << 3) + 6) << kOpcodeShift,
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| -
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| -  COP1X     =   ((1 << 4) + 3) << kOpcodeShift
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| +  SPECIAL = 0 << kOpcodeShift,
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| +  REGIMM = 1 << kOpcodeShift,
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| +
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| +  J = ((0 << 3) + 2) << kOpcodeShift,
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| +  JAL = ((0 << 3) + 3) << kOpcodeShift,
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| +  BEQ = ((0 << 3) + 4) << kOpcodeShift,
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| +  BNE = ((0 << 3) + 5) << kOpcodeShift,
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| +  BLEZ = ((0 << 3) + 6) << kOpcodeShift,
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| +  BGTZ = ((0 << 3) + 7) << kOpcodeShift,
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| +
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| +  ADDI = ((1 << 3) + 0) << kOpcodeShift,
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| +  ADDIU = ((1 << 3) + 1) << kOpcodeShift,
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| +  SLTI = ((1 << 3) + 2) << kOpcodeShift,
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| +  SLTIU = ((1 << 3) + 3) << kOpcodeShift,
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| +  ANDI = ((1 << 3) + 4) << kOpcodeShift,
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| +  ORI = ((1 << 3) + 5) << kOpcodeShift,
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| +  XORI = ((1 << 3) + 6) << kOpcodeShift,
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| +  LUI = ((1 << 3) + 7) << kOpcodeShift,  // LUI/AUI family.
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| +
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| +  BEQC = ((2 << 3) + 0) << kOpcodeShift,
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| +  COP1 = ((2 << 3) + 1) << kOpcodeShift,  // Coprocessor 1 class.
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| +  BEQL = ((2 << 3) + 4) << kOpcodeShift,
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| +  BNEL = ((2 << 3) + 5) << kOpcodeShift,
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| +  BLEZL = ((2 << 3) + 6) << kOpcodeShift,
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| +  BGTZL = ((2 << 3) + 7) << kOpcodeShift,
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| +
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| +  DADDI = ((3 << 3) + 0) << kOpcodeShift,  // This is also BNEC.
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| +  SPECIAL2 = ((3 << 3) + 4) << kOpcodeShift,
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| +  SPECIAL3 = ((3 << 3) + 7) << kOpcodeShift,
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| +
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| +  LB = ((4 << 3) + 0) << kOpcodeShift,
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| +  LH = ((4 << 3) + 1) << kOpcodeShift,
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| +  LWL = ((4 << 3) + 2) << kOpcodeShift,
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| +  LW = ((4 << 3) + 3) << kOpcodeShift,
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| +  LBU = ((4 << 3) + 4) << kOpcodeShift,
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| +  LHU = ((4 << 3) + 5) << kOpcodeShift,
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| +  LWR = ((4 << 3) + 6) << kOpcodeShift,
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| +  SB = ((5 << 3) + 0) << kOpcodeShift,
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| +  SH = ((5 << 3) + 1) << kOpcodeShift,
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| +  SWL = ((5 << 3) + 2) << kOpcodeShift,
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| +  SW = ((5 << 3) + 3) << kOpcodeShift,
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| +  SWR = ((5 << 3) + 6) << kOpcodeShift,
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| +
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| +  LWC1 = ((6 << 3) + 1) << kOpcodeShift,
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| +  BC = ((6 << 3) + 2) << kOpcodeShift,
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| +  LDC1 = ((6 << 3) + 5) << kOpcodeShift,
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| +  POP66 = ((6 << 3) + 6) << kOpcodeShift,
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| +
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| +  PREF = ((6 << 3) + 3) << kOpcodeShift,
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| +
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| +  SWC1 = ((7 << 3) + 1) << kOpcodeShift,
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| +  BALC = ((7 << 3) + 2) << kOpcodeShift,
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| +  PCREL = ((7 << 3) + 3) << kOpcodeShift,
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| +  SDC1 = ((7 << 3) + 5) << kOpcodeShift,
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| +  POP76 = ((7 << 3) + 6) << kOpcodeShift,
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| +
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| +  COP1X = ((1 << 4) + 3) << kOpcodeShift
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|  };
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|  
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|  enum SecondaryField {
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| @@ -435,7 +447,14 @@ enum SecondaryField {
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|    // SPECIAL3 Encoding of Function Field.
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|    EXT = ((0 << 3) + 0),
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|    INS = ((0 << 3) + 4),
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| -  BITSWAP = ((4 << 3) + 0),
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| +  BSHFL = ((4 << 3) + 0),
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| +
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| +  // SPECIAL3 Encoding of sa Field.
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| +  BITSWAP = ((0 << 3) + 0),
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| +  ALIGN = ((0 << 3) + 2),
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| +  WSBH = ((0 << 3) + 2),
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| +  SEB = ((2 << 3) + 0),
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| +  SEH = ((3 << 3) + 0),
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|  
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|    // REGIMM  encoding of rt Field.
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|    BLTZ = ((0 << 3) + 0) << 16,
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| @@ -571,6 +590,18 @@ enum SecondaryField {
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|    // COP1X Encoding of Function Field.
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|    MADD_D = ((4 << 3) + 1),
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|  
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| +  // PCREL Encoding of rt Field.
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| +  ADDIUPC = ((0 << 2) + 0),
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| +  LWPC = ((0 << 2) + 1),
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| +  AUIPC = ((3 << 3) + 6),
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| +  ALUIPC = ((3 << 3) + 7),
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| +
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| +  // POP66 Encoding of rs Field.
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| +  JIC = ((0 << 5) + 0),
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| +
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| +  // POP76 Encoding of rs Field.
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| +  JIALC = ((0 << 5) + 0),
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| +
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|    NULLSF = 0
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|  };
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|  
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| @@ -881,6 +912,11 @@ class Instruction {
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|      return Bits(kFrShift + kFrBits -1, kFrShift);
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|    }
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|  
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| +  inline int Bp2Value() const {
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| +    DCHECK(InstructionType() == kRegisterType);
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| +    return Bits(kBp2Shift + kBp2Bits - 1, kBp2Shift);
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| +  }
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| +
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|    // Float Compare condition code instruction bits.
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|    inline int FCccValue() const {
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|      return Bits(kFCccShift + kFCccBits - 1, kFCccShift);
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| @@ -924,7 +960,6 @@ class Instruction {
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|    }
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|  
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|    inline int SaFieldRaw() const {
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| -    DCHECK(InstructionType() == kRegisterType);
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|      return InstructionBits() & kSaFieldMask;
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|    }
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|  
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| @@ -953,13 +988,24 @@ class Instruction {
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|      return Bits(kImm16Shift + kImm16Bits - 1, kImm16Shift);
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|    }
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|  
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| +  inline int32_t Imm18Value() const {
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| +    DCHECK(InstructionType() == kImmediateType);
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| +    return Bits(kImm18Shift + kImm18Bits - 1, kImm18Shift);
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| +  }
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| +
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| +  inline int32_t Imm19Value() const {
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| +    DCHECK(InstructionType() == kImmediateType);
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| +    return Bits(kImm19Shift + kImm19Bits - 1, kImm19Shift);
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| +  }
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| +
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|    inline int32_t Imm21Value() const {
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|      DCHECK(InstructionType() == kImmediateType);
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|      return Bits(kImm21Shift + kImm21Bits - 1, kImm21Shift);
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|    }
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|  
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|    inline int32_t Imm26Value() const {
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| -    DCHECK(InstructionType() == kJumpType);
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| +    DCHECK((InstructionType() == kJumpType) ||
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| +           (InstructionType() == kImmediateType));
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|      return Bits(kImm26Shift + kImm26Bits - 1, kImm26Shift);
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|    }
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|  
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| 
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