MIPS: Implemented PC-relative instructions for R6.

test/cctest/test-disasm-mips64.cc

Index: test/cctest/test-disasm-mips64.cc
diff --git a/test/cctest/test-disasm-mips64.cc b/test/cctest/test-disasm-mips64.cc
index 4d0b44024ca65777cebc1e8f532f3e4288b10258..8f5f3be4f35cb3a415d540748669cdb3250d4817 100644
--- a/test/cctest/test-disasm-mips64.cc
+++ b/test/cctest/test-disasm-mips64.cc
@@ -685,6 +685,72 @@ TEST(Type0) {
   COMPARE(div_s(f2, f4, f6), "46062083       div.s   f2, f4, f6");
   COMPARE(div_d(f2, f4, f6), "46262083       div.d   f2, f4, f6");
 
+  if (kArchVariant == kMips64r6) {
+    COMPARE(align(v0, a0, a1, 0), "7c851220       align  v0, a0, a1, 0");
+    COMPARE(align(v0, a0, a1, 1), "7c851260       align  v0, a0, a1, 1");
+    COMPARE(align(v0, a0, a1, 2), "7c8512a0       align  v0, a0, a1, 2");
+    COMPARE(align(v0, a0, a1, 3), "7c8512e0       align  v0, a0, a1, 3");
+  }
+
+  if (kArchVariant == kMips64r6) {
+    COMPARE(dalign(v0, a0, a1, 0), "7c851224       dalign  v0, a0, a1, 0");
+    COMPARE(dalign(v0, a0, a1, 1), "7c851264       dalign  v0, a0, a1, 1");
+    COMPARE(dalign(v0, a0, a1, 2), "7c8512a4       dalign  v0, a0, a1, 2");
+    COMPARE(dalign(v0, a0, a1, 3), "7c8512e4       dalign  v0, a0, a1, 3");
+    COMPARE(dalign(v0, a0, a1, 4), "7c851324       dalign  v0, a0, a1, 4");
+    COMPARE(dalign(v0, a0, a1, 5), "7c851364       dalign  v0, a0, a1, 5");
+    COMPARE(dalign(v0, a0, a1, 6), "7c8513a4       dalign  v0, a0, a1, 6");
+    COMPARE(dalign(v0, a0, a1, 7), "7c8513e4       dalign  v0, a0, a1, 7");
+  }
+
+  if (kArchVariant == kMips64r6) {
+    COMPARE(aluipc(v0, 0), "ec5f0000       aluipc  v0, 0");
+    COMPARE(aluipc(v0, 1), "ec5f0001       aluipc  v0, 1");
+    COMPARE(aluipc(v0, 32767), "ec5f7fff       aluipc  v0, 32767");
+    COMPARE(aluipc(v0, -32768), "ec5f8000       aluipc  v0, -32768");
+    COMPARE(aluipc(v0, -1), "ec5fffff       aluipc  v0, -1");
+  }
+
+  if (kArchVariant == kMips64r6) {
+    COMPARE(lwpc(a5, 0), "ed280000       lwpc    a5, 0");
+    COMPARE(lwpc(a5, 4), "ed280004       lwpc    a5, 4");
+    COMPARE(lwpc(a5, -4), "ed2ffffc       lwpc    a5, -4");
+  }
+
+  if (kArchVariant == kMips64r6) {
+    COMPARE(jic(t0, 16), "d80c0010       jic     t0, 16");
+    COMPARE(jic(t0, 4), "d80c0004       jic     t0, 4");
+    COMPARE(jic(t0, -32), "d80cffe0       jic     t0, -32");
+  }
+
+  if (kArchVariant == kMips64r6) {
+    COMPARE(beqzc(a0, 16), "d8800010       beqzc   a0, 0x10");
+    COMPARE(beqzc(a0, 4), "d8800004       beqzc   a0, 0x4");
+    COMPARE(beqzc(a0, -32), "d89fffe0       beqzc   a0, 0x1fffe0");
+  }
+
+  if (kArchVariant == kMips64r6) {
+    COMPARE(ldpc(v0, 256), "ec580100       ldpc    v0, 256");
+    COMPARE(ldpc(a0, -1), "ec9bffff       ldpc    a0, -1");
+    COMPARE(ldpc(a1, 0), "ecb80000       ldpc    a1, 0");
+  }
+
+  if (kArchVariant == kMips64r6) {
+    COMPARE(addiupc(a0, 262143), "ec83ffff       addiupc a0, 262143");
+    COMPARE(addiupc(a0, -1), "ec87ffff       addiupc a0, -1");
+    COMPARE(addiupc(v0, 0), "ec400000       addiupc v0, 0");
+    COMPARE(addiupc(s1, 1), "ee200001       addiupc s1, 1");
+    COMPARE(addiupc(a0, -262144), "ec840000       addiupc a0, -262144");
+  }
+
+  if (kArchVariant == kMips64r6) {
+    COMPARE(jialc(a0, -32768), "f8048000       jialc   a0, 0x8000");
+    COMPARE(jialc(a0, -1), "f804ffff       jialc   a0, 0xffff");
+    COMPARE(jialc(v0, 0), "f8020000       jialc   v0, 0x0");
+    COMPARE(jialc(s1, 1), "f8110001       jialc   s1, 0x1");
+    COMPARE(jialc(a0, 32767), "f8047fff       jialc   a0, 0x7fff");
+  }
+
   VERIFY_RUN();
 }