MIPS: Implemented PC-relative instructions for R6.

src/mips/assembler-mips.cc

Index: src/mips/assembler-mips.cc
diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc
index 50732026b09667d870dd00effd0880efeedbadb4..0fa98192d742e959a041b90919bf416c3fe3a3f0 100644
--- a/src/mips/assembler-mips.cc
+++ b/src/mips/assembler-mips.cc
@@ -282,7 +282,6 @@ const Instr kLwSwInstrTypeMask = 0xffe00000;
 const Instr kLwSwInstrArgumentMask  = ~kLwSwInstrTypeMask;
 const Instr kLwSwOffsetMask = kImm16Mask;
 
-
 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
     : AssemblerBase(isolate, buffer, buffer_size),
       recorded_ast_id_(TypeFeedbackId::None()),
@@ -959,6 +958,14 @@ void Assembler::GenInstrImmediate(Opcode opcode,
 }
 
 
+void Assembler::GenInstrImmediate(Opcode opcode, Register rs, int32_t j) {
+  DCHECK(rs.is_valid() && (is_uint21(j)));
+  Instr instr =
+      opcode | (rs.code() << kRsShift) | static_cast<uint32_t>(j & kImm21Mask);
+  emit(instr);
+}
+
+
 void Assembler::GenInstrJump(Opcode opcode,
                              uint32_t address) {
   BlockTrampolinePoolScope block_trampoline_pool(this);
@@ -1355,7 +1362,8 @@ void Assembler::beqc(Register rs, Register rt, int16_t offset) {
 void Assembler::beqzc(Register rs, int32_t offset) {
   DCHECK(IsMipsArchVariant(kMips32r6));
   DCHECK(!(rs.is(zero_reg)));
-  Instr instr = BEQZC | (rs.code() << kRsShift) | offset;
+  Instr instr = POP66 | (rs.code() << kRsShift) |
+                static_cast<uint32_t>(offset & kImm21Mask);
   emit(instr);
 }
 
@@ -1370,7 +1378,7 @@ void Assembler::bnec(Register rs, Register rt, int16_t offset) {
 void Assembler::bnezc(Register rs, int32_t offset) {
   DCHECK(IsMipsArchVariant(kMips32r6));
   DCHECK(!(rs.is(zero_reg)));
-  Instr instr = BNEZC | (rs.code() << kRsShift) | offset;
+  Instr instr = POP76 | (rs.code() << kRsShift) | offset;
   emit(instr);
 }
 
@@ -1448,6 +1456,21 @@ void Assembler::jal_or_jalr(int32_t target, Register rs) {
 }
 
 
+void Assembler::jic(Register rt, int16_t offset) {
+  DCHECK(kArchVariant == kMips32r6);
+  Instr instr = POP66 | (JIC << kRsShift) | (rt.code() << kRtShift) |
+                static_cast<uint16_t>(offset);
+  emit(instr);
+}
+
+
+void Assembler::jialc(Register rt, int16_t offset) {
+  DCHECK(kArchVariant == kMips32r6);
+  positions_recorder()->WriteRecordedPositions();
+  GenInstrImmediate(POP76, zero_reg, rt, offset);
+}
+
+
 // -------Data-processing-instructions---------
 
 // Arithmetic.
@@ -1762,6 +1785,37 @@ void Assembler::aui(Register rs, Register rt, int32_t j) {
 }
 
 
+// ---------PC-Relative instructions-----------
+
+void Assembler::addiupc(Register rs, int32_t imm19) {
+  DCHECK(kArchVariant == kMips32r6);
+  DCHECK(rs.is_valid());
+  DCHECK((kMinInt19 <= imm19) && (imm19 <= kMaxInt19));
+  int32_t imm21 =
+      ADDIUPC << kImm19Bits | static_cast<uint32_t>(imm19 & kImm19Mask);
+  GenInstrImmediate(PCREL, rs, imm21);
+}
+
+
+void Assembler::lwpc(Register rs, int32_t offset19) {
+  DCHECK(kArchVariant == kMips32r6);
+  DCHECK(rs.is_valid());
+  DCHECK((kMinInt19 <= offset19) && (offset19 <= kMaxInt19));
+  int32_t imm21 =
+      LWPC << kImm19Bits | static_cast<uint32_t>(offset19 & kImm19Mask);
+  GenInstrImmediate(PCREL, rs, imm21);
+}
+
+
+void Assembler::aluipc(Register rs, int16_t imm16) {
+  DCHECK(kArchVariant == kMips32r6);
+  DCHECK(rs.is_valid() && is_int16(imm16));
+  int32_t imm21 =
+      ALUIPC << kImm16Bits | static_cast<uint32_t>(imm16 & kImm16Mask);
+  GenInstrImmediate(PCREL, rs, imm21);
+}
+
+
 // -------------Misc-instructions--------------
 
 // Break / Trap instructions.
@@ -1938,7 +1992,7 @@ void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) {
 
 void Assembler::bitswap(Register rd, Register rt) {
   DCHECK(kArchVariant == kMips32r6);
-  GenInstrRegister(SPECIAL3, zero_reg, rt, rd, 0, BITSWAP);
+  GenInstrRegister(SPECIAL3, zero_reg, rt, rd, 0, BSHFL);
 }
 
 
@@ -1951,6 +2005,14 @@ void Assembler::pref(int32_t hint, const MemOperand& rs) {
 }
 
 
+void Assembler::align(Register rd, Register rs, Register rt, uint8_t bp) {
+  DCHECK(kArchVariant == kMips32r6);
+  DCHECK(is_uint3(bp));
+  uint16_t sa = (ALIGN << kBp2Bits) | bp;
+  GenInstrRegister(SPECIAL3, rs, rt, rd, sa, BSHFL);
+}
+
+
 // --------Coprocessor-instructions----------------
 
 // Load, store, move.