MIPS: Implemented PC-relative instructions for R6.

src/mips/simulator-mips.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #include "src/v8.h"
@@ skipping 2151 matching lines @@
   // Instruction fields.
   const Opcode   op     = instr->OpcodeFieldRaw();
   const int32_t  rs_reg = instr->RsValue();
   const int32_t  rs     = get_register(rs_reg);
   const uint32_t rs_u   = static_cast<uint32_t>(rs);
   const int32_t  rt_reg = instr->RtValue();
   const int32_t  rt     = get_register(rt_reg);
   const uint32_t rt_u   = static_cast<uint32_t>(rt);
   const int32_t  rd_reg = instr->RdValue();
   const uint32_t sa     = instr->SaValue();
+  const uint8_t bp = instr->Bp2Value();
 
   const int32_t  fs_reg = instr->FsValue();
 
 
   // ---------- Configuration.
   switch (op) {
     case COP1:    // Coprocessor instructions.
       switch (instr->RsFieldRaw()) {
         case CFC1:
           // At the moment only FCSR is supported.
@@ skipping 222 matching lines @@
         case EXT: {   // Mips32r2 instruction.
           // Interpret rd field as 5-bit msb of extract.
           uint16_t msb = rd_reg;
           // Interpret sa field as 5-bit lsb of extract.
           uint16_t lsb = sa;
           uint16_t size = msb + 1;
           uint32_t mask = (1 << size) - 1;
           *alu_out = (rs_u & (mask << lsb)) >> lsb;
           break;
         }
-        case BITSWAP: {  // Mips32r6 instruction
-          uint32_t input = static_cast<uint32_t>(rt);
-          uint32_t output = 0;
-          uint8_t i_byte, o_byte;
+        case BSHFL: {
+          int sa = instr->SaFieldRaw() >> kSaShift;
+          switch (sa) {
+            case BITSWAP: {
+              uint32_t input = static_cast<uint32_t>(rt);
+              uint32_t output = 0;
+              uint8_t i_byte, o_byte;
 
-          // Reverse the bit in byte for each individual byte
-          for (int i = 0; i < 4; i++) {
-            output = output >> 8;
-            i_byte = input & 0xff;
+              // Reverse the bit in byte for each individual byte
+              for (int i = 0; i < 4; i++) {
+                output = output >> 8;
+                i_byte = input & 0xff;
 
-            // Fast way to reverse bits in byte
-            // Devised by Sean Anderson, July 13, 2001
-            o_byte = static_cast<uint8_t>(((i_byte * 0x0802LU & 0x22110LU) |
-                                           (i_byte * 0x8020LU & 0x88440LU)) *
-                                              0x10101LU >>
-                                          16);
+                // Fast way to reverse bits in byte
+                // Devised by Sean Anderson, July 13, 2001
+                o_byte =
+                    static_cast<uint8_t>(((i_byte * 0x0802LU & 0x22110LU) |
+                                          (i_byte * 0x8020LU & 0x88440LU)) *
+                                             0x10101LU >>
+                                         16);
 
-            output = output | (static_cast<uint32_t>(o_byte << 24));
-            input = input >> 8;
+                output = output | (static_cast<uint32_t>(o_byte << 24));
+                input = input >> 8;
+              }
+
+              *alu_out = static_cast<int32_t>(output);
+              break;
+            }
+            case SEB:
+            case SEH:
+            case WSBH:
+              UNREACHABLE();
+              break;
+            default: {
+              sa >>= kBp2Bits;
+              switch (sa) {
+                case ALIGN: {
+                  if (bp == 0) {
+                    *alu_out = static_cast<int32_t>(rt);
+                  } else {
+                    uint32_t rt_hi = rt << (8 * bp);
+                    uint32_t rs_lo = rs >> (8 * (4 - bp));
+                    *alu_out = static_cast<int32_t>(rt_hi | rs_lo);
+                  }
+                  break;
+                }
+                default:
+                  UNREACHABLE();
+                  break;
+              }
+            }
           }
-
-          *alu_out = static_cast<int32_t>(output);
           break;
         }
         default:
           UNREACHABLE();
       }
       break;
     default:
       UNREACHABLE();
   }
 }
@@ skipping 1307 matching lines @@
 void Simulator::DecodeTypeRegisterSPECIAL3(Instruction* instr,
                                            const int32_t& rt_reg,
                                            const int32_t& rd_reg,
                                            int32_t& alu_out) {
   switch (instr->FunctionFieldRaw()) {
     case INS:
       // Ins instr leaves result in Rt, rather than Rd.
       set_register(rt_reg, alu_out);
       break;
     case EXT:
-      // Ext instr leaves result in Rt, rather than Rd.
       set_register(rt_reg, alu_out);
       break;
-    case BITSWAP:
+    case BSHFL:
       set_register(rd_reg, alu_out);
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegister(Instruction* instr) {
   // Instruction fields.
@@ skipping 64 matching lines @@
     default:
       set_register(rd_reg, alu_out);
   }
 }
 
 
 // Type 2: instructions using a 16 bytes immediate. (e.g. addi, beq).
 void Simulator::DecodeTypeImmediate(Instruction* instr) {
   // Instruction fields.
   Opcode   op     = instr->OpcodeFieldRaw();
+  int32_t rs_reg = instr->RsValue();
   int32_t  rs     = get_register(instr->RsValue());
   uint32_t rs_u   = static_cast<uint32_t>(rs);
   int32_t  rt_reg = instr->RtValue();  // Destination register.
   int32_t  rt     = get_register(rt_reg);
   int16_t  imm16  = instr->Imm16Value();
+  int32_t imm19 = instr->Imm19Value();
+  int32_t imm21 = instr->Imm21Value();
+  int32_t imm26 = instr->Imm26Value();
 
   int32_t  ft_reg = instr->FtValue();  // Destination register.
   int64_t  ft;
 
   // Zero extended immediate.
   uint32_t  oe_imm16 = 0xffff & imm16;
   // Sign extended immediate.
-  int32_t   se_imm16 = imm16;
+  int32_t se_imm16 = imm16;
+  int32_t se_imm19 = imm19 | ((imm19 & 0x40000) ? 0xfff80000 : 0);
+  int32_t se_imm26 = imm26 | ((imm26 & 0x2000000) ? 0xfc000000 : 0);
+
 
   // Get current pc.
   int32_t current_pc = get_pc();
   // Next pc.
   int32_t next_pc = bad_ra;
+  // pc increment
+  int16_t pc_increment;
 
   // Used for conditional branch instructions.
   bool do_branch = false;
   bool execute_branch_delay_instruction = false;
 
   // Used for arithmetic instructions.
   int32_t alu_out = 0;
   // Floating point.
   double fp_out = 0.0;
   uint32_t cc, cc_value, fcsr_cc;
@@ skipping 93 matching lines @@
       break;
     case BNE:
       do_branch = rs != rt;
       break;
     case BLEZ:
       do_branch = rs <= 0;
       break;
     case BGTZ:
       do_branch = rs  > 0;
       break;
+    case POP66: {
+      if (rs_reg) {  // BEQZC
+        int32_t se_imm21 =
+            static_cast<int32_t>(imm21 << (kOpcodeBits + kRsBits));
+        se_imm21 = se_imm21 >> (kOpcodeBits + kRsBits);
+        if (rs == 0)
+          next_pc = current_pc + 4 + (se_imm21 << 2);
+        else
+          next_pc = current_pc + 4;
+      } else {  // JIC
+        next_pc = rt + imm16;
+      }
+      break;
+    }
+    case BC: {
+      next_pc = current_pc + 4 + (se_imm26 << 2);
+      set_pc(next_pc);
+      pc_modified_ = true;
+      break;
+    }
+    case BALC: {
+      set_register(31, current_pc + 4);
+      next_pc = current_pc + 4 + (se_imm26 << 2);
+      set_pc(next_pc);
+      pc_modified_ = true;
+      break;
+    }
     // ------------- Arithmetic instructions.
     case ADDI:
       if (HaveSameSign(rs, se_imm16)) {
         if (rs > 0) {
           exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue - se_imm16);
         } else if (rs < 0) {
           exceptions[kIntegerUnderflow] =
               rs < (Registers::kMinValue - se_imm16);
         }
       }
@@ skipping 94 matching lines @@
       alu_out = ReadW(addr, instr);
       break;
     case LDC1:
       addr = rs + se_imm16;
       fp_out = ReadD(addr, instr);
       break;
     case SWC1:
     case SDC1:
       addr = rs + se_imm16;
       break;
+    // ------------- JIALC and BNEZC instructions.
+    case POP76:
+      // Next pc.
+      next_pc = rt + se_imm16;
+      // The instruction after the jump is NOT executed.
+      pc_increment = Instruction::kInstrSize;
+      if (instr->IsLinkingInstruction()) {
+        set_register(31, current_pc + pc_increment);
+      }
+      set_pc(next_pc);
+      pc_modified_ = true;
+      break;
+    // ------------- PC-Relative instructions.
+    case PCREL: {
+      // rt field: checking 5-bits.
+      uint8_t rt = (imm21 >> kImm16Bits);
+      switch (rt) {
+        case ALUIPC:
+          addr = current_pc + (se_imm16 << 16);
+          alu_out = static_cast<int64_t>(~0x0FFFF) & addr;
+          break;
+        case AUIPC:
+          alu_out = current_pc + (se_imm16 << 16);
+          break;
+        default: {
+          // rt field: checking the most significant 2-bits.
+          rt = (imm21 >> kImm19Bits);
+          switch (rt) {
+            case LWPC: {
+              int32_t offset = imm19;
+              // Set sign.
+              offset <<= (kOpcodeBits + kRsBits + 2);
+              offset >>= (kOpcodeBits + kRsBits + 2);
+              addr = current_pc + (offset << 2);
+              uint32_t* ptr = reinterpret_cast<uint32_t*>(addr);
+              alu_out = *ptr;
+              break;
+            }
+            case ADDIUPC:
+              alu_out = current_pc + (se_imm19 << 2);
+              break;
+            default:
+              UNREACHABLE();
+              break;
+          }
+        }
+      }
+      break;
+    }
     default:
       UNREACHABLE();
   }
 
   // ---------- Raise exceptions triggered.
   SignalExceptions();
 
   // ---------- Execution.
   switch (op) {
     // ------------- Branch instructions.
@@ skipping 57 matching lines @@
       set_fpu_register_double(ft_reg, fp_out);
       break;
     case SWC1:
       addr = rs + se_imm16;
       WriteW(addr, get_fpu_register_word(ft_reg), instr);
       break;
     case SDC1:
       addr = rs + se_imm16;
       WriteD(addr, get_fpu_register_double(ft_reg), instr);
       break;
+    case PCREL:
+      set_register(rs_reg, alu_out);
     default:
       break;
   }
 
 
   if (execute_branch_delay_instruction) {
     // Execute branch delay slot
     // We don't check for end_sim_pc. First it should not be met as the current
     // pc is valid. Secondly a jump should always execute its branch delay slot.
     Instruction* branch_delay_instr =
@@ skipping 248 matching lines @@
 
 
 #undef UNSUPPORTED
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_MIPS